BUAA Computer_Organizations Projects

Author: ComradeProgrammer

p3/P3.docx

@@ -0,0 +1,14 @@
+`timescale 1ns / 1ps
+
+module ALU(a,b,aluop,aluout);
+input [31:0]a,b;
+input [1:0] aluop;
+output [31:0] aluout;
+
+wire [31:0] tmp[3:0];
+assign tmp[1]=a+b;
+assign tmp[2]=a-b;
+assign tmp[3]=a|b;
+assign aluout=tmp[aluop];
+
+endmodule

p3/P3.pdf

@@ -0,0 +1,14 @@
+`timescale 1ns / 1ps
+
+module CMP(a,b,zero32,gtz32,gez32,ltz32,lez32);
+input [31:0]a,b;
+output [31:0] zero32,gtz32,gez32,ltz32,lez32;
+
+assign zero32=(a==b)?32'h1:32'h0;
+
+assign gtz32=($signed(a)>$signed(b))?32'b1:32'b0;
+assign gez32=($signed(a)>=$signed(b))?32'b1:32'b0;
+assign ltz32=($signed(a)<$signed(b))?32'b1:32'b0;
+assign lez32=($signed(a)<=$signed(b))?32'b1:32'b0;
+
+endmodule

p3/p3/p3_final.circ

@@ -0,0 +1,68 @@
+`timescale 1ns / 1ps
+`include "head.v"
+module DATAPATH(clk,clr,
+branch,regwrite,memwrite,npcop,extop,aluop,alusrc,hf,bt,
+regdst,memtoreg,
+isbeq,isbgtz,isbgez,isbltz,isblez,
+issll,issra,issrl,v,
+instr);
+input clk,clr,branch,regwrite,memwrite,isbeq,alusrc,hf,bt,isbgtz,isbgez,isbltz,isblez,issra,issrl,issll,v;
+input [1:0] npcop,extop,aluop,regdst;
+input [2:0] memtoreg;
+output[31:0] instr;
+//==================mux=====================================
+wire [4:0]regaddr;
+wire [31:0] regdata,alubdata;
+//==================wire declearation=======================
+wire [31:0]pc4;
+wire [31:0] rd1,rd2,extout,zero32,npcout,gtz32,gez32,ltz32,lez32,shiftout;
+wire [31:0] aluout;
+wire [31:0] dmout;
+wire branchlogic;
+//===================instr fetch============================
+IM im(.clk(clk),.clr(clr),.branch(branchlogic),.npc(npcout),.instr(instr),.pc4(pc4));
+assign branchlogic=(branch&isbeq&zero32[0])|(branch&isbgtz&gtz32[0])|(branch&isbgez&gez32[0])|(branch&isbltz&ltz32[0])
+							|(branch&isblez&lez32[0])|(branch&~isbeq&~isbgtz&~isbgtz&~isbgez&~isbltz&~isblez);
+//=====================decode===============================
+wire [4:0] rs,rd,rt,shamt;
+wire [5:0] op,funct;
+wire [15:0] imm;
+assign op=instr[31:26];
+assign funct=instr[5:0];
+assign shamt=instr[10:6];
+assign rd=instr[15:11];
+assign rt=instr[20:16];
+assign rs=instr[25:21];
+assign imm=instr[15:0];
+GPR gpr(.clk(clk),.clr(clr),.we(regwrite),.a1(rs),.a2(rt),.a3(regaddr),.wd(regdata),.rd1(rd1),.rd2(rd2));
+EXT ext(.imm(imm),.extop(extop),.extout(extout));
+CMP cmp(.a(rd1),.b(rd2),.zero32(zero32),.gtz32(gtz32),.gez32(gez32),.ltz32(ltz32),.lez32(lez32));
+NPC npc(.pc4(pc4),.extout(extout),.instr(instr),.rd1(rd1),.npcop(npcop),.npcout(npcout));
+shift sft(rd2,rd1,shamt,issll,issrl,issra,v,shiftout);
+
+//========================execute===============================
+ALU alu(.a(rd1),.b(alubdata),.aluop(aluop),.aluout(aluout));
+assign alubdata=(alusrc==`alusrc_rd2)?rd2:extout;
+//======================memory==================================
+DM dm(.clk(clk),.clr(clr),.we(memwrite),.addr(aluout),.wd(rd2),.dmout(dmout),.hf(hf),.bt(bt));
+//========================writeback===================================
+assign regaddr= (regdst==`regdst_rd)?rd:
+					  (regdst==`regdst_rt)?rt:
+					  5'd31;
+					  
+					  
+					  
+assign regdata=   (memtoreg==`mtr_slti)?($signed(rd1)<$signed(extout))?32'b1:32'b0:
+						(memtoreg==`mtr_shift)?shiftout:
+						(memtoreg==`mtr_slt)?(($signed(rd1)<$signed(rd2))?32'b1:32'b0):
+						(memtoreg==`mtr_alu)?aluout:
+						(memtoreg==`mtr_dm)?dmout:
+						(memtoreg==`mtr_ext)?extout:
+						pc4;
+//================================================================================
+
+
+
+
+
+endmodule

p4/P4/ALU.v

@@ -0,0 +1,63 @@
+`timescale 1ns / 1ps
+
+module DM(clk,clr,we,addr,wd,dmout,hf,bt);
+input clk,clr,we,hf,bt;
+input [31:0] addr,wd;
+output [31:0]dmout;
+
+reg [31:0] dmmem[1023:0];
+integer i;
+wire [31:0] word,wdin;
+wire [31:0] hfword[1:0],hfin[1:0];
+wire [31:0]btword[3:0],btin[3:0];
+
+
+
+assign word=dmmem[addr[11:2]];
+assign hfword[0]={16'b0,word[15:0]};
+assign hfword[1]={16'b0,word[31:16]};
+assign btword [0]={24'b0,word[7:0]};
+assign btword [1]={24'b0,word[15:8]};
+assign btword [2]={24'b0,word[23:16]};
+assign btword [3]={24'b0,word[31:24]};
+
+
+assign hfin[0]={word[31:16],wd[15:0]};
+assign hfin[1]={wd[15:0],word[15:0]};
+assign btin[0]={word[31:24],word[23:16],word[15:8],wd[7:0]};
+assign btin[1]={word[31:24],word[23:16],wd[7:0],word[7:0]};
+assign btin[2]={word[31:24],wd[7:0],word[15:8],word[7:0]};
+assign btin[3]={wd[7:0],word[23:16],word[15:8],word[7:0]};
+
+assign wdin=(hf==1)?hfin[addr[1]]:
+				(bt==1)?btin[addr[1:0]]:
+				wd;
+
+initial begin
+	for(i=0;i<1024;i=i+1)
+		dmmem[i]<=0;
+end
+
+
+always@(posedge clk)
+	begin
+		if(clr)
+			begin
+				for(i=0;i<1024;i=i+1)
+					dmmem[i]<=0;
+			end
+		else
+			begin
+				if(we)
+					begin
+						dmmem[addr[11:2]]<=wdin;
+						$display("@%h: *%h <= %h",im.pc, {addr[31:2],2'b00},wdin);//xian fang zheli
+					end
+			end
+	end
+
+
+assign dmout=(hf==1)?hfword[addr[1]]:
+					(bt==1)?btword[addr[1:0]]:
+					word;
+endmodule

p4/P4/CMP.v

@@ -0,0 +1,14 @@
+`timescale 1ns / 1ps
+
+module EXT(imm,extop,extout);
+input [15:0]imm;
+input [1:0] extop;
+output [31:0] extout;
+
+wire [31:0]tmp[3:0];
+assign tmp[0]={16'b0,imm};
+assign tmp[1]={{16{imm[15]}},imm};
+assign tmp[2]={imm,16'b0};
+assign extout=tmp[extop];
+
+endmodule

p4/P4/DATAPATH.v

@@ -0,0 +1,36 @@
+`timescale 1ns / 1ps
+
+module GPR(clk,clr,we,a1,a2,a3,wd,rd1,rd2);
+input clk,clr,we;
+input [31:0] wd;
+input [4:0] a1,a2,a3;
+output [31:0] rd1,rd2;
+reg[31:0] regmem[31:0];
+
+integer i;
+initial begin
+	for(i=0;i<32;i=i+1)
+		regmem[i]<=0;
+end
+
+always@(posedge clk)
+	begin
+		if(clr)
+			begin
+				for(i=0;i<31;i=i+1)
+					regmem[i]<=0;
+			end
+		else
+			begin
+				if(we==1&&a3!=0)
+					begin
+						regmem[a3]<=wd;
+						$display("@%h: $%d <= %h", im.pc,a3,wd);//output display,xian fang zhe li
+					end
+			end
+	end
+
+assign rd1=regmem[a1];
+assign rd2=regmem[a2];
+
+endmodule

p4/P4/DM.v

@@ -0,0 +1,44 @@
+`timescale 1ns / 1ps
+
+module IM(clk,clr,branch,npc,instr,pc4);
+input clk,clr,branch;
+input [31:0] npc;
+output [31:0] instr,pc4;
+
+reg [31:0]pc;
+reg [31:0] inmem[1023:0];
+integer i;
+
+wire [31:0]pointer;
+initial begin
+	for(i=0;i<1024;i=i+1)
+		inmem[i]=0;
+	pc=32'h0003000;
+	$readmemh("code.txt",inmem,0,1023);
+end
+
+
+
+always @(posedge clk)
+	begin
+		if(clr)
+			begin
+				for(i=0;i<1024;i=i+1)
+					inmem[i]=0;
+				$readmemh("code.txt",inmem,0,1023);
+				pc<=32'h00003000;
+			end
+		else
+			begin
+				if(branch==1)
+					pc<=npc;
+				else
+					pc<=pc+4;
+			end
+	end
+	
+assign pc4=pc+4;
+assign pointer=pc-32'h00003000;
+assign instr=inmem[pointer[31:2]];
+	
+endmodule

p4/P4/EXT.v

@@ -0,0 +1,15 @@
+`timescale 1ns / 1ps
+
+module NPC(pc4,extout,instr,rd1,npcop,npcout);
+input [31:0] pc4,extout,instr,rd1;
+input [1:0] npcop;
+output [31:0] npcout;
+
+wire [31:0]tmp[3:0];
+wire [31:0]offset;
+assign offset={extout[29:0],2'b00};
+assign tmp[0]=pc4+offset;
+assign tmp[1]={pc4[31:28],instr[25:0],2'b00};
+assign tmp[2]=rd1;
+assign npcout=tmp[npcop];
+endmodule