diff --git a/VHDL/adc/adc.vhd b/VHDL/adc/adc.vhd index ff7b652..ef20a63 100644 --- a/VHDL/adc/adc.vhd +++ b/VHDL/adc/adc.vhd @@ -1,10 +1,13 @@ ---------------------------------------------------------------------------------------------------- --- brief: This VHDL file implements the full ADC. --- file: tdc.vhd +-- brief: This file implements a slope ADC which uses the output impedance in the ouput buffers to +-- create a reference slope which is then compared to the signal-to-be-measured. A TDC +-- measures the time from the beginning of the slope until the slope crosses the voltage-to- +-- be-measured. Different linearization and correction techniques are also deployed. +-- file: adc.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/calcMean/calcMean.vhd b/VHDL/calcMean/calcMean.vhd index 3eea352..0297c49 100644 --- a/VHDL/calcMean/calcMean.vhd +++ b/VHDL/calcMean/calcMean.vhd @@ -1,10 +1,10 @@ ---------------------------------------------------------------------------------------------------- --- project Calculates the mean over n samples --- file calcMean.vhd --- author Lukas Leuenberger +-- brief: This block calcualtes the mean values over n samples. +-- file: calcMean.vhd +-- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/calcMean/calcMean_tb.vhd b/VHDL/calcMean/calcMean_tb.vhd index 5fe8356..b53ca19 100644 --- a/VHDL/calcMean/calcMean_tb.vhd +++ b/VHDL/calcMean/calcMean_tb.vhd @@ -3,8 +3,8 @@ -- file: calcMean_tb.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/calibrationTDCAlign/calibrationTDCAlign.vhd b/VHDL/calibrationTDCAlign/calibrationTDCAlign.vhd index a17b544..3d0f87e 100644 --- a/VHDL/calibrationTDCAlign/calibrationTDCAlign.vhd +++ b/VHDL/calibrationTDCAlign/calibrationTDCAlign.vhd @@ -1,10 +1,10 @@ ---------------------------------------------------------------------------------------------------- --- brief: calibrationTDCAlign - Führt den Kalibrationsvorgang für den TDC aus +-- brief: This block calibrates the aligning of the delay chain with the slope. -- file: calibrationTDCAlign.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/calibrationTDCAlign/calibrationTDCAlign_tb.vhd b/VHDL/calibrationTDCAlign/calibrationTDCAlign_tb.vhd index 18284b2..162012c 100644 --- a/VHDL/calibrationTDCAlign/calibrationTDCAlign_tb.vhd +++ b/VHDL/calibrationTDCAlign/calibrationTDCAlign_tb.vhd @@ -3,8 +3,8 @@ -- file: calibrationTDCAlign_tb.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/calibrationTDCLength/calibrationTDCLength.vhd b/VHDL/calibrationTDCLength/calibrationTDCLength.vhd index a97544f..cc8ce40 100644 --- a/VHDL/calibrationTDCLength/calibrationTDCLength.vhd +++ b/VHDL/calibrationTDCLength/calibrationTDCLength.vhd @@ -1,10 +1,11 @@ ---------------------------------------------------------------------------------------------------- --- brief: calibrationTDCLength - Führt den Kalibrationsvorgang für den TDC aus +-- brief: This block calibrates the length of the delay chain, eg. the number of taps which +-- correspond to one clock period are determined. -- file: calibrationTDCLength.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/calibrationTDCLength/calibrationTDCLength_tb.vhd b/VHDL/calibrationTDCLength/calibrationTDCLength_tb.vhd index 56e5f7c..6e5cb52 100644 --- a/VHDL/calibrationTDCLength/calibrationTDCLength_tb.vhd +++ b/VHDL/calibrationTDCLength/calibrationTDCLength_tb.vhd @@ -3,8 +3,8 @@ -- file: calibrationTDCLength_tb.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/carryChain/carryChain.vhd b/VHDL/carryChain/carryChain.vhd index 37ff883..f43e2d2 100644 --- a/VHDL/carryChain/carryChain.vhd +++ b/VHDL/carryChain/carryChain.vhd @@ -1,10 +1,10 @@ ---------------------------------------------------------------------------------------------------- --- brief: carryChain - Carry Chain +-- brief: This block implements a carry chain. -- file: carryChain.vhd -- author: Felix Haller, Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) -- This VHDL code is initially based on code written by h.a.r.homulle@tudelft.nl found on http://cas.tudelft.nl/fpga_tdc/TDC_basic.html ---------------------------------------------------------------------------------------------------- -- File history: diff --git a/VHDL/carryDelay/carryDelay.vhd b/VHDL/carryDelay/carryDelay.vhd index 7b146b5..81b973a 100644 --- a/VHDL/carryDelay/carryDelay.vhd +++ b/VHDL/carryDelay/carryDelay.vhd @@ -1,10 +1,10 @@ ---------------------------------------------------------------------------------------------------- --- brief: carryDelay - Applies a configurable delay before the signal enters the carry chain +-- brief: This block applies a configurable delay before the signal enters the carry chain. -- file: carryDelay.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/diffInputPad/diffInputPad.vhd b/VHDL/diffInputPad/diffInputPad.vhd index 7053208..956f1e4 100644 --- a/VHDL/diffInputPad/diffInputPad.vhd +++ b/VHDL/diffInputPad/diffInputPad.vhd @@ -1,10 +1,11 @@ ---------------------------------------------------------------------------------------------------- --- brief: diffInputPad +-- brief: This block instantiates the differential input/output buffer which is used to generate the +-- reference slope and which contains also the comparator. -- file: diffInputPad.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/division/division.vhd b/VHDL/division/division.vhd index 79a70ec..9975cea 100644 --- a/VHDL/division/division.vhd +++ b/VHDL/division/division.vhd @@ -1,10 +1,10 @@ ---------------------------------------------------------------------------------------------------- --- project: Division +-- project: This block performs a division from two values. -- file: division.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/division/divison_tb.vhd b/VHDL/division/divison_tb.vhd index 3673902..a75192b 100644 --- a/VHDL/division/divison_tb.vhd +++ b/VHDL/division/divison_tb.vhd @@ -1,11 +1,10 @@ ---------------------------------------------------------------------------------------------------- --- project: Division - Testbench -- brief: Testbench for the Division block -- file: divison_tb.vhd --- author: Marco Ehrler +-- author: Marco Ehrler, Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/dnl/dnl.vhd b/VHDL/dnl/dnl.vhd index d195f42..62df3ee 100644 --- a/VHDL/dnl/dnl.vhd +++ b/VHDL/dnl/dnl.vhd @@ -1,10 +1,10 @@ ---------------------------------------------------------------------------------------------------- --- brief: DNL - Berechnet die DNL aus einem Histogram +-- brief: Calculates the DNL from a histogram. -- file: dnl.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/dnl/dnl_tb.vhd b/VHDL/dnl/dnl_tb.vhd index 4f81b06..f6464db 100644 --- a/VHDL/dnl/dnl_tb.vhd +++ b/VHDL/dnl/dnl_tb.vhd @@ -3,8 +3,8 @@ -- file: dnl_tb.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/histogram/histogram.vhd b/VHDL/histogram/histogram.vhd index 000e498..cb988af 100644 --- a/VHDL/histogram/histogram.vhd +++ b/VHDL/histogram/histogram.vhd @@ -1,10 +1,10 @@ ---------------------------------------------------------------------------------------------------- --- brief: Histogram - Calculates a histogram +-- brief: This block calculates a histogram. -- file: hitsogram.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/histogram/histogram_tb.vhd b/VHDL/histogram/histogram_tb.vhd index 01f3672..98efe25 100644 --- a/VHDL/histogram/histogram_tb.vhd +++ b/VHDL/histogram/histogram_tb.vhd @@ -3,8 +3,8 @@ -- file: histogram_tb.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/inl/inl.vhd b/VHDL/inl/inl.vhd index b47ac91..ad51027 100644 --- a/VHDL/inl/inl.vhd +++ b/VHDL/inl/inl.vhd @@ -1,10 +1,10 @@ ---------------------------------------------------------------------------------------------------- --- brief: INL - Calculates the INL from a DNL +-- brief: Calculates the INL from a DNL. -- file: inl.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/inl/inl_tb.vhd b/VHDL/inl/inl_tb.vhd index 4facd7c..71c8d34 100644 --- a/VHDL/inl/inl_tb.vhd +++ b/VHDL/inl/inl_tb.vhd @@ -3,8 +3,8 @@ -- file: inl_tb.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/inlCorrection/inlCorrection.vhd b/VHDL/inlCorrection/inlCorrection.vhd index 46a689a..3cc622d 100644 --- a/VHDL/inlCorrection/inlCorrection.vhd +++ b/VHDL/inlCorrection/inlCorrection.vhd @@ -3,8 +3,8 @@ -- file: inlCorrection.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/inlCorrection/inlCorrectionCalc.vhd b/VHDL/inlCorrection/inlCorrectionCalc.vhd index 15f7d02..0fc24b3 100644 --- a/VHDL/inlCorrection/inlCorrectionCalc.vhd +++ b/VHDL/inlCorrection/inlCorrectionCalc.vhd @@ -3,8 +3,8 @@ -- file: inlCorrectionCalc.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/inlCorrection/inlCorrectionCalc_tb.vhd b/VHDL/inlCorrection/inlCorrectionCalc_tb.vhd index 1095208..34254ee 100644 --- a/VHDL/inlCorrection/inlCorrectionCalc_tb.vhd +++ b/VHDL/inlCorrection/inlCorrectionCalc_tb.vhd @@ -3,8 +3,8 @@ -- file: inlCorrectionCalc_tb.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/inlCorrection/inlCorrectionControl.vhd b/VHDL/inlCorrection/inlCorrectionControl.vhd index 67013fc..20e901f 100644 --- a/VHDL/inlCorrection/inlCorrectionControl.vhd +++ b/VHDL/inlCorrection/inlCorrectionControl.vhd @@ -3,8 +3,8 @@ -- file: inlCorrectionControl.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/inlCorrection/inlCorrectionControl_tb.vhd b/VHDL/inlCorrection/inlCorrectionControl_tb.vhd index 49e5059..7d4ddeb 100644 --- a/VHDL/inlCorrection/inlCorrectionControl_tb.vhd +++ b/VHDL/inlCorrection/inlCorrectionControl_tb.vhd @@ -3,8 +3,8 @@ -- file: inlCorrectionControl_tb.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/lutTransition/lutTransition.vhd b/VHDL/lutTransition/lutTransition.vhd index 5bfd8cf..d17d13f 100644 --- a/VHDL/lutTransition/lutTransition.vhd +++ b/VHDL/lutTransition/lutTransition.vhd @@ -1,10 +1,11 @@ ---------------------------------------------------------------------------------------------------- --- brief: lutTransition - Looks up the corrected value for an input signal and calculates the output value based on this +-- brief: Looks up the corrected value for an input signal and calculates the output value based on +-- this value. -- file: lutTransition.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/lutTransition/lutTransition_tb.vhd b/VHDL/lutTransition/lutTransition_tb.vhd index a7f3476..6195625 100644 --- a/VHDL/lutTransition/lutTransition_tb.vhd +++ b/VHDL/lutTransition/lutTransition_tb.vhd @@ -3,8 +3,8 @@ -- file: lutTransition_tb.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/pulseDelay/pulseDelay.vhd b/VHDL/pulseDelay/pulseDelay.vhd index 48d8772..d6d2f7c 100644 --- a/VHDL/pulseDelay/pulseDelay.vhd +++ b/VHDL/pulseDelay/pulseDelay.vhd @@ -1,10 +1,10 @@ ---------------------------------------------------------------------------------------------------- --- brief: carryDelay - Applies a configurable delay before the signal enters the carry chain --- file: carryDelay.vhd +-- brief: Applies a configurable delay before the clock exits the FPGA through the output buffer +-- file: pulseDelay.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/tdc/tdc.vhd b/VHDL/tdc/tdc.vhd index e60a920..7d8fb68 100644 --- a/VHDL/tdc/tdc.vhd +++ b/VHDL/tdc/tdc.vhd @@ -3,8 +3,8 @@ -- file: tdc.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/tdc/tdcSingle.vhd b/VHDL/tdc/tdcSingle.vhd index 34a7490..df9c049 100644 --- a/VHDL/tdc/tdcSingle.vhd +++ b/VHDL/tdc/tdcSingle.vhd @@ -3,8 +3,8 @@ -- file: tdcSingle.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/tdpRAM/tdpRAM.vhd b/VHDL/tdpRAM/tdpRAM.vhd index 40aaf88..1851e56 100644 --- a/VHDL/tdpRAM/tdpRAM.vhd +++ b/VHDL/tdpRAM/tdpRAM.vhd @@ -1,16 +1,16 @@ ---------------------------------------------------------------------------------------------------- --- project True dual port ram --- file tdpRAM.vhd --- author Lukas Leuenberger +-- brief: True dual port ram +-- file: tdpRAM.vhd +-- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- --- File history: +-- File history: -- --- Version | Date | Author | Remarks --- ------------------------------------------------------------------------------------------------ --- 0.1 | 08.04.2020 | L. Leuenberger | Created +-- Version | Date | Author | Remarks +-- ------------------------------------------------------------------------------------------------- +-- 0.1 | 08.04.2020 | L. Leuenberger | Created ---------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------ diff --git a/VHDL/transitionDetector/transitionDetector.vhd b/VHDL/transitionDetector/transitionDetector.vhd index 02da893..3514be4 100644 --- a/VHDL/transitionDetector/transitionDetector.vhd +++ b/VHDL/transitionDetector/transitionDetector.vhd @@ -1,11 +1,11 @@ ---------------------------------------------------------------------------------------------------- --- brief: Transition Detector - Detects up to two transitions in the carry chain output +-- brief: Detects up to two transitions (one rising and one falling) in the carry chain output -- Partially based on an implementation from Dorian Amiet -- file: transitionDetector.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/transitionDetector/transitionDetector_tb.vhd b/VHDL/transitionDetector/transitionDetector_tb.vhd index 0111a83..ef34e92 100644 --- a/VHDL/transitionDetector/transitionDetector_tb.vhd +++ b/VHDL/transitionDetector/transitionDetector_tb.vhd @@ -3,8 +3,8 @@ -- file: transitionDetector_tb.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/writeDRP/writeDRP.vhd b/VHDL/writeDRP/writeDRP.vhd index 0a66296..86c1edb 100644 --- a/VHDL/writeDRP/writeDRP.vhd +++ b/VHDL/writeDRP/writeDRP.vhd @@ -1,10 +1,10 @@ ---------------------------------------------------------------------------------------------------- --- brief: writeDRP - Writes a register of the MMCM over the DRP interface --- file: carryDelay.vhd +-- brief: Writes a register of the MMCM over the DRP interface +-- file: writeDRP.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: -- diff --git a/VHDL/writeDRP/writeDRP_tb.vhd b/VHDL/writeDRP/writeDRP_tb.vhd index 7e89d95..4e668b5 100644 --- a/VHDL/writeDRP/writeDRP_tb.vhd +++ b/VHDL/writeDRP/writeDRP_tb.vhd @@ -3,8 +3,8 @@ -- file: writeDRP_tb.vhd -- author: Lukas Leuenberger ---------------------------------------------------------------------------------------------------- --- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences --- All rights reserved. +-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch) +-- This code is licensed under the MIT license (see LICENSE for details) ---------------------------------------------------------------------------------------------------- -- File history: --