branch and files updated

Author: Nimit3-droid

Course_Project_report_B6.pdf

@@ -1,9 +1,9 @@
 
 module	liftcontroller(start,clk,reset_inside_button,reset_up,reset_down,up_button,down_button,inside_button,present_floor); 
 	input start,clk;
-	input [6:0] up_button,down_button,inside_button;
-	output [6:0] reset_inside_button,reset_up,reset_down,present_floor;
-	reg [6:0] reset_inside_button,reset_up,reset_down,present_floor;
+	input [4:0] up_button,down_button,inside_button;
+	output [4:0] reset_inside_button,reset_up,reset_down,present_floor;
+	reg [4:0] reset_inside_button,reset_up,reset_down,present_floor;
 	reg dir_up;
 	reg [4:0] nstate;
       	parameter 	s0_idle=0,s0_up=1,door_0=2,s1_idle=3,s1_up=4,s1_down=5,

Inputs/sample_input1.v

@@ -3,25 +3,25 @@
 
 module rlencoding(data_in,data_in_valid,fast_clk,data_clk,reset,data_out,data_out_valid,read_signal,write_signal,readptr,writeptr,output1,data_clk1);
 
-	input [7:0] data_in;
+	input [4:0] data_in;
 	input read_signal,write_signal,fast_clk,data_clk,data_in_valid,reset,data_clk1;
-	output reg [7:0] data_out;
+	output reg [4:0] data_out;
 	output data_out_valid;
-	output [7:0] readptr,writeptr;
+	output [4:0] readptr,writeptr;
 	output [2:0] output1;
 
 	reg [7:0] buffer [0:255];
-	reg [7:0] count;
-	reg [7:0] bufferoutput;
-	reg [7:0] readptr;
-	reg [7:0] writeptr;
+	reg [4:0] count;
+	reg [4:0] bufferoutput;
+	reg [4:0] readptr;
+	reg [4:0] writeptr;
 	reg [1:0] nstate;
-	reg [7:0] datacount;
+	reg [4:0] datacount;
 	reg [2:0] output1;
 	reg equal_or_not;
-	reg [7:0] buffer1;
-	reg [7:0] buffer2;
-	reg [7:0] buffer3;
+	reg [4:0] buffer1;
+	reg [4:0] buffer2;
+	reg [4:0] buffer3;
 	reg flag1;
 	reg flag2;
 	reg flag3;

Inputs/sample_input7.v

@@ -19,7 +19,7 @@ module usbf_pa(	clk, rst,
 input		clk, rst;
 
 // UTMI TX Interface
-output	[7:0]	tx_data;
+output	[4:0]	tx_data;
 output		tx_valid;
 output		tx_valid_last;
 input		tx_ready;
@@ -33,7 +33,7 @@ input	[1:0]	data_pid_sel;
 input		send_zero_length;
 
 // IDMA Interface
-input	[7:0]	tx_data_st;
+input	[4:0]	tx_data_st;
 output		rd_next;
 
 ///////////////////////////////////////////////////////////////////
@@ -54,20 +54,20 @@ reg	[4:0]	/* synopsys enum state */ state, next_state;
 reg		last;
 reg		rd_next;
 
-reg	[7:0]	token_pid, data_pid;	// PIDs from selectors
-reg	[7:0]	tx_data_d;
-reg	[7:0]	tx_data_data;
+reg	[4:0]	token_pid, data_pid;	// PIDs from selectors
+reg	[4:0]	tx_data_d;
+reg	[4:0]	tx_data_data;
 reg		dsel;
 reg		tx_valid_d;
 reg		send_token_r;
-reg	[7:0]	tx_spec_data;
+reg	[4:0]	tx_spec_data;
 reg		crc_sel1, crc_sel2;
 reg		tx_first_r;
 reg		send_data_r;
 wire		crc16_clr;
-reg	[15:0]	crc16;
-wire	[15:0]	crc16_next;
-wire	[15:0]	crc16_rev;
+reg	[4:0]	crc16;
+wire	[4:0]	crc16_next;
+wire	[4:0]	crc16_rev;
 wire		crc16_add;
 reg		send_data_r2;
 reg		tx_valid_r;
@@ -141,8 +141,8 @@ always @(dsel or tx_data_st or tx_spec_data)
 always @(crc_sel1 or crc_sel2 or data_pid or crc16_rev)
 	if(!crc_sel1 && !crc_sel2)	tx_spec_data = data_pid;
 	else
-	if(crc_sel1)			tx_spec_data = crc16_rev[15:8];	// CRC 1
-	else				tx_spec_data = crc16_rev[7:0];	// CRC 2
+	if(crc_sel1)			tx_spec_data = crc16_rev[4:4];	// CRC 1
+	else				tx_spec_data = crc16_rev[4:0];	// CRC 2
 
 assign tx_data = tx_data_d;
 

Outputs/abstracted_model1.v

@@ -27,7 +27,7 @@ module usbf_pd(	clk, rst,
 input		clk, rst;
 
 		//UTMI RX Interface
-input	[7:0]	rx_data;
+input	[4:0]	rx_data;
 input		rx_valid, rx_active, rx_err;
 
 		// Decoded PIDs (used when token_valid is asserted)
@@ -38,13 +38,13 @@ output		pid_PRE, pid_ERR, pid_SPLIT, pid_PING;
 output		pid_cks_err;		// Indicates a PID checksum error
 
 
-output	[6:0]	token_fadr;		// Function address from token
-output	[3:0]	token_endp;		// Endpoint number from token
+output	[4:0]	token_fadr;		// Function address from token
+output	[2:0]	token_endp;		// Endpoint number from token
 output		token_valid;		// Token is valid
 output		crc5_err;		// Token crc5 error
-output	[10:0]	frame_no;		// Frame number for SOF tokens
+output	[4:0]	frame_no;		// Frame number for SOF tokens
 
-output	[7:0]	rx_data_st;		// Data to memory store unit
+output	[4:0]	rx_data_st;		// Data to memory store unit
 output		rx_data_valid;		// Data on rx_data_st is valid
 output		rx_data_done;		// Indicates end of a transfer
 output		crc16_err;		// Data packet CRC 16 error
@@ -56,16 +56,16 @@ output		seq_err;		// State Machine Sequence Error
 // Local Wires and Registers
 //
 
-parameter	[3:0]	// synopsys enum state
+parameter	[2:0]	// synopsys enum state
 		IDLE   = 4'b0001,
 		ACTIVE = 4'b0010,
 		TOKEN  = 4'b0100,
 		DATA   = 4'b1000;
 
-reg	[3:0]	/* synopsys enum state */ state, next_state;
+reg	[2:0]	/* synopsys enum state */ state, next_state;
 // synopsys state_vector state
 
-reg	[7:0]	pid;			// Packet PDI
+reg	[4:0]	pid;			// Packet PDI
 reg		pid_le_sm;		// PID Load enable from State Machine
 wire		pid_ld_en;		// Enable loading of PID (all conditions)
 wire		pid_cks_err;		// Indicates a pid checksum err
@@ -78,11 +78,11 @@ wire		pid_PRE, pid_ERR, pid_SPLIT, pid_PING, pid_RES;
 wire		pid_TOKEN;		// All TOKEN packet that we recognize
 wire		pid_DATA;		// All DATA packets that we recognize
 
-reg	[7:0]	token0, token1;		// Token Registers
+reg	[4:0]	token0, token1;		// Token Registers
 reg		token_le_1, token_le_2;	// Latch enables for token storage registers
 wire	[4:0]	token_crc5;
 
-reg	[7:0]	d0, d1, d2;		// Data path delay line (used to filter out crcs)
+reg	[4:0]	d0, d1, d2;		// Data path delay line (used to filter out crcs)
 reg		data_valid_d;		// Data Valid output from State Machine
 reg		data_done;		// Data cycle complete output from State Machine
 reg		data_valid0; 		// Data valid delay line
@@ -101,8 +101,8 @@ reg		rx_active_r;
 wire	[4:0]	crc5_out;
 wire	[4:0]	crc5_out2;
 wire		crc16_clr;
-reg	[15:0]	crc16_sum;
-wire	[15:0]	crc16_out;
+reg	[4:0]	crc16_sum;
+wire	[4:0]	crc16_out;
 
 ///////////////////////////////////////////////////////////////////
 //
@@ -123,23 +123,23 @@ always @(posedge clk)
 
 assign	pid_cks_err = (pid[3:0] != ~pid[7:4]);
 
-assign	pid_OUT   = pid[3:0] == `USBF_T_PID_OUT;
-assign	pid_IN    = pid[3:0] == `USBF_T_PID_IN;
-assign	pid_SOF   = pid[3:0] == `USBF_T_PID_SOF;
-assign	pid_SETUP = pid[3:0] == `USBF_T_PID_SETUP;
-assign	pid_DATA0 = pid[3:0] == `USBF_T_PID_DATA0;
-assign	pid_DATA1 = pid[3:0] == `USBF_T_PID_DATA1;
-assign	pid_DATA2 = pid[3:0] == `USBF_T_PID_DATA2;
-assign	pid_MDATA = pid[3:0] == `USBF_T_PID_MDATA;
-assign	pid_ACK   = pid[3:0] == `USBF_T_PID_ACK;
-assign	pid_NACK  = pid[3:0] == `USBF_T_PID_NACK;
-assign	pid_STALL = pid[3:0] == `USBF_T_PID_STALL;
-assign	pid_NYET  = pid[3:0] == `USBF_T_PID_NYET;
-assign	pid_PRE   = pid[3:0] == `USBF_T_PID_PRE;
-assign	pid_ERR   = pid[3:0] == `USBF_T_PID_ERR;
-assign	pid_SPLIT = pid[3:0] == `USBF_T_PID_SPLIT;
-assign	pid_PING  = pid[3:0] == `USBF_T_PID_PING;
-assign	pid_RES   = pid[3:0] == `USBF_T_PID_RES;
+assign	pid_OUT   = pid[2:0] == `USBF_T_PID_OUT;
+assign	pid_IN    = pid[2:0] == `USBF_T_PID_IN;
+assign	pid_SOF   = pid[2:0] == `USBF_T_PID_SOF;
+assign	pid_SETUP = pid[2:0] == `USBF_T_PID_SETUP;
+assign	pid_DATA0 = pid[2:0] == `USBF_T_PID_DATA0;
+assign	pid_DATA1 = pid[2:0] == `USBF_T_PID_DATA1;
+assign	pid_DATA2 = pid[2:0] == `USBF_T_PID_DATA2;
+assign	pid_MDATA = pid[2:0] == `USBF_T_PID_MDATA;
+assign	pid_ACK   = pid[2:0] == `USBF_T_PID_ACK;
+assign	pid_NACK  = pid[2:0] == `USBF_T_PID_NACK;
+assign	pid_STALL = pid[2:0] == `USBF_T_PID_STALL;
+assign	pid_NYET  = pid[2:0] == `USBF_T_PID_NYET;
+assign	pid_PRE   = pid[2:0] == `USBF_T_PID_PRE;
+assign	pid_ERR   = pid[2:0] == `USBF_T_PID_ERR;
+assign	pid_SPLIT = pid[2:0] == `USBF_T_PID_SPLIT;
+assign	pid_PING  = pid[2:0] == `USBF_T_PID_PING;
+assign	pid_RES   = pid[2:0] == `USBF_T_PID_RES;
 
 assign	pid_TOKEN = pid_OUT | pid_IN | pid_SOF | pid_SETUP | pid_PING;
 assign	pid_DATA = pid_DATA0 | pid_DATA1 | pid_DATA2 | pid_MDATA;