gzll: nRF5340 network core support

GZLL support for nRF5340 network core.

Signed-off-by: Bernard Lee <bernard.lee@nordicsemi.no>

Author: leewkb4567

gzll/Kconfig

@@ -6,4 +6,4 @@
 
 config GZLL
 	bool "Enable Gazell Link Layer"
-	depends on SOC_SERIES_NRF52X
+	depends on SOC_SERIES_NRF52X || SOC_SERIES_NRF53X

gzll/include/nrf_gzll_constants.h

@@ -42,6 +42,7 @@ extern "C" {
 /*
  * PPI configuration
  */
+#if defined(PPI_PRESENT) || defined(DOXYGEN)
 #define NRF_GZLL_PPI_EEP0 (*nrf_gzll_ppi_eep0)                      ///< Gazell PPI event endpoint 0
 #define NRF_GZLL_PPI_TEP0 (*nrf_gzll_ppi_tep0)                      ///< Gazell PPI task endpoint 0
 #define NRF_GZLL_PPI_EEP1 (*nrf_gzll_ppi_eep1)                      ///< Gazell PPI event endpoint 1
@@ -51,6 +52,16 @@ extern "C" {
 
 #define NRF_GZLL_PPI_CHEN_MSK_0_AND_1 (nrf_gzll_ppi_chen_msk_0_and_1) ///< Channel enable/disable mask for PPI endpoint 0 and 1.
 #define NRF_GZLL_PPI_CHEN_MSK_2       (nrf_gzll_ppi_chen_msk_2)       ///< Channel enable/disable mask for PPI endpoint 2.
+#endif
+
+#if defined(DPPI_PRESENT) || defined(DOXYGEN)
+#define NRF_GZLL_DPPI_CH0 (nrf_gzll_dppi_ch0)                       ///< Gazell DPPI channel 0
+#define NRF_GZLL_DPPI_CH1 (nrf_gzll_dppi_ch1)                       ///< Gazell DPPI channel 1
+#define NRF_GZLL_DPPI_CH2 (nrf_gzll_dppi_ch2)                       ///< Gazell DPPI channel 2
+
+#define NRF_GZLL_DPPI_CHEN_MSK_0_AND_1 (nrf_gzll_dppi_chen_msk_0_and_1) ///< Channel enable/disable mask for DPPI channel 0 and 1.
+#define NRF_GZLL_DPPI_CHEN_MSK_2       (nrf_gzll_dppi_chen_msk_2)       ///< Channel enable/disable mask for DPPI channel 2.
+#endif
 /** @} */
 
 /*****************************************************************************/

gzll/include/nrf_gzll_glue.h

@@ -15,6 +15,7 @@
  */
 
 #include <nrf.h>
+#include <nrf_peripherals.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -38,6 +39,7 @@ extern IRQn_Type        const nrf_gzll_timer_irqn;
 /** Interrupt number for the software interrupt. */
 extern IRQn_Type        const nrf_gzll_swi_irqn;
 
+#if defined(PPI_PRESENT) || defined(DOXYGEN)
 /** Gazell PPI event endpoint 0 register address. */
 extern __IOM uint32_t * nrf_gzll_ppi_eep0;
 /** Gazell PPI task endpoint 0 register address. */
@@ -54,6 +56,20 @@ extern __IOM uint32_t * nrf_gzll_ppi_tep2;
 extern       uint32_t   nrf_gzll_ppi_chen_msk_0_and_1;
 /** Channel enable/disable mask for PPI endpoint 2. */
 extern       uint32_t   nrf_gzll_ppi_chen_msk_2;
+#endif
+
+#if defined(DPPI_PRESENT) || defined(DOXYGEN)
+/** Gazell DPPI channel index 0. */
+extern uint8_t nrf_gzll_dppi_ch0;
+/** Gazell DPPI channel index 1. */
+extern uint8_t nrf_gzll_dppi_ch1;
+/** Gazell DPPI channel index 2. */
+extern uint8_t nrf_gzll_dppi_ch2;
+/** Channel enable/disable mask for DPPI channel 0 and 1. */
+extern uint32_t nrf_gzll_dppi_chen_msk_0_and_1;
+/** Channel enable/disable mask for DPPI channel 2. */
+extern uint32_t nrf_gzll_dppi_chen_msk_2;
+#endif
 
 
 /**