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rossbergrossberg
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Merge pull request #515 from WebAssembly/refactor.spec
[spec] Refactor spec to align with interpreter
2 parents 02cf939 + a288cc7 commit b9fbe20

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-898
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‎document/core/appendix/gen-index-instructions.py

+70-70
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‎document/core/appendix/index-instructions.rst

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‎document/core/appendix/index-types.rst

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@@ -12,8 +12,8 @@ Category Constructor
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:ref:`Number type <syntax-numtype>` |I64| :math:`\hex{7E}` (-2 as |Bs7|)
1313
:ref:`Number type <syntax-numtype>` |F32| :math:`\hex{7D}` (-3 as |Bs7|)
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:ref:`Number type <syntax-numtype>` |F64| :math:`\hex{7C}` (-4 as |Bs7|)
15-
:ref:`Number type <syntax-numtype>` |V128| :math:`\hex{7B}` (-5 as |Bs7|)
16-
(reserved) :math:`\hex{7B}` .. :math:`\hex{71}`
15+
:ref:`Number type <syntax-vectype>` |V128| :math:`\hex{7B}` (-5 as |Bs7|)
16+
(reserved) :math:`\hex{7A}` .. :math:`\hex{71}`
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:ref:`Reference type <syntax-reftype>` |FUNCREF| :math:`\hex{70}` (-16 as |Bs7|)
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:ref:`Reference type <syntax-reftype>` |EXTERNREF| :math:`\hex{6F}` (-17 as |Bs7|)
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(reserved) :math:`\hex{6E}` .. :math:`\hex{61}`

‎document/core/binary/instructions.rst

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@@ -461,17 +461,17 @@ whereas the actual opcode is encoded by a variable-length :ref:`unsigned integer
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\end{array}
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.. index:: simd instruction
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.. index:: vector instruction
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pair: binary format; instruction
466-
.. _binary-instr-simd:
466+
.. _binary-instr-vec:
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468-
SIMD Instructions
469-
~~~~~~~~~~~~~~~~~~~~
468+
Vector Instructions
469+
~~~~~~~~~~~~~~~~~~~
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471-
All variants of :ref:`SIMD instructions <syntax-instr-simd>` are represented by separate byte codes.
471+
All variants of :ref:`vector instructions <syntax-instr-vec>` are represented by separate byte codes.
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They all have a one byte prefix, whereas the actual opcode is encoded by a variable-length :ref:`unsigned integer <binary-uint>`.
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474-
SIMD loads and stores are followed by the encoding of their |memarg| immediate.
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Vector loads and stores are followed by the encoding of their |memarg| immediate.
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.. _binary-laneidx:
477477

@@ -544,11 +544,11 @@ The |SHUFFLE| instruction is also followed by the encoding of 16 |laneidx| immed
544544
\hex{FD}~~34{:}\Bu32~~l{:}\Blaneidx &\Rightarrow& \F64X2.\REPLACELANE~l \\
545545
\end{array}
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547-
All other SIMD instructions are plain opcodes without any immediates.
547+
All other vector instructions are plain opcodes without any immediates.
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.. math::
550550
\begin{array}{llclll}
551-
\production{instruction} & \Binstr &::=& \dots && \phantom{simdhaslongerinstructionnames} \\&&|&
551+
\production{instruction} & \Binstr &::=& \dots && \phantom{vechaslongerinstructionnames} \\&&|&
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\hex{FD}~~14{:}\Bu32 &\Rightarrow& \I8X16.\SWIZZLE \\ &&|&
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\hex{FD}~~15{:}\Bu32 &\Rightarrow& \I8X16.\SPLAT \\ &&|&
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\hex{FD}~~16{:}\Bu32 &\Rightarrow& \I16X8.\SPLAT \\ &&|&
@@ -562,7 +562,7 @@ All other SIMD instructions are plain opcodes without any immediates.
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.. math::
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\begin{array}{llclll}
565-
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
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\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
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\hex{FD}~~35{:}\Bu32 &\Rightarrow& \I8X16.\VEQ \\ &&|&
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\hex{FD}~~36{:}\Bu32 &\Rightarrow& \I8X16.\VNE \\ &&|&
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\hex{FD}~~37{:}\Bu32 &\Rightarrow& \I8X16.\VLT\K{\_s} \\ &&|&
@@ -577,7 +577,7 @@ All other SIMD instructions are plain opcodes without any immediates.
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.. math::
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\begin{array}{llclll}
580-
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
580+
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
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\hex{FD}~~45{:}\Bu32 &\Rightarrow& \I16X8.\VEQ \\ &&|&
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\hex{FD}~~46{:}\Bu32 &\Rightarrow& \I16X8.\VNE \\ &&|&
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\hex{FD}~~47{:}\Bu32 &\Rightarrow& \I16X8.\VLT\K{\_s} \\ &&|&
@@ -592,7 +592,7 @@ All other SIMD instructions are plain opcodes without any immediates.
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.. math::
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\begin{array}{llclll}
595-
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
595+
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
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\hex{FD}~~55{:}\Bu32 &\Rightarrow& \I32X4.\VEQ \\ &&|&
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\hex{FD}~~56{:}\Bu32 &\Rightarrow& \I32X4.\VNE \\ &&|&
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\hex{FD}~~57{:}\Bu32 &\Rightarrow& \I32X4.\VLT\K{\_s} \\ &&|&
@@ -607,7 +607,7 @@ All other SIMD instructions are plain opcodes without any immediates.
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.. math::
609609
\begin{array}{llclll}
610-
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
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\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
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\hex{FD}~~214{:}\Bu32 &\Rightarrow& \I64X2.\VEQ \\ &&|&
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\hex{FD}~~215{:}\Bu32 &\Rightarrow& \I64X2.\VNE \\ &&|&
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\hex{FD}~~216{:}\Bu32 &\Rightarrow& \I64X2.\VLT\K{\_s} \\ &&|&
@@ -620,7 +620,7 @@ All other SIMD instructions are plain opcodes without any immediates.
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.. math::
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\begin{array}{llclll}
623-
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
623+
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
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\hex{FD}~~65{:}\Bu32 &\Rightarrow& \F32X4.\VEQ \\ &&|&
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\hex{FD}~~66{:}\Bu32 &\Rightarrow& \F32X4.\VNE \\ &&|&
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\hex{FD}~~67{:}\Bu32 &\Rightarrow& \F32X4.\VLT \\ &&|&
@@ -631,7 +631,7 @@ All other SIMD instructions are plain opcodes without any immediates.
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.. math::
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\begin{array}{llclll}
634-
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
634+
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
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\hex{FD}~~71{:}\Bu32 &\Rightarrow& \F64X2.\VEQ \\ &&|&
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\hex{FD}~~72{:}\Bu32 &\Rightarrow& \F64X2.\VNE \\ &&|&
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\hex{FD}~~73{:}\Bu32 &\Rightarrow& \F64X2.\VLT \\ &&|&
@@ -646,7 +646,7 @@ All other SIMD instructions are plain opcodes without any immediates.
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647647
.. math::
648648
\begin{array}{llclll}
649-
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
649+
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
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\hex{FD}~~77{:}\Bu32 &\Rightarrow& \V128.\VNOT \\ &&|&
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\hex{FD}~~78{:}\Bu32 &\Rightarrow& \V128.\VAND \\ &&|&
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\hex{FD}~~79{:}\Bu32 &\Rightarrow& \V128.\VANDNOT \\ &&|&
@@ -665,7 +665,7 @@ All other SIMD instructions are plain opcodes without any immediates.
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.. math::
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\begin{array}{llclll}
668-
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
668+
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
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\hex{FD}~~96{:}\Bu32 &\Rightarrow& \I8X16.\VABS \\ &&|&
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\hex{FD}~~97{:}\Bu32 &\Rightarrow& \I8X16.\VNEG \\ &&|&
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\hex{FD}~~98{:}\Bu32 &\Rightarrow& \I8X16.\VPOPCNT \\ &&|&
@@ -691,7 +691,7 @@ All other SIMD instructions are plain opcodes without any immediates.
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.. math::
693693
\begin{array}{llclll}
694-
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
694+
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
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\hex{FD}~~124{:}\Bu32 &\Rightarrow& \I16X8.\EXTADDPAIRWISE\K{\_i8x16\_s}\\ &&|&
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\hex{FD}~~125{:}\Bu32 &\Rightarrow& \I16X8.\EXTADDPAIRWISE\K{\_i8x16\_u}\\ &&|&
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\hex{FD}~~128{:}\Bu32 &\Rightarrow& \I16X8.\VABS \\ &&|&
@@ -728,7 +728,7 @@ All other SIMD instructions are plain opcodes without any immediates.
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.. math::
730730
\begin{array}{llclll}
731-
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
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\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
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\hex{FD}~~126{:}\Bu32 &\Rightarrow& \I32X4.\EXTADDPAIRWISE\K{\_i16x8\_s}\\ &&|&
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\hex{FD}~~127{:}\Bu32 &\Rightarrow& \I32X4.\EXTADDPAIRWISE\K{\_i16x8\_u}\\ &&|&
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\hex{FD}~~160{:}\Bu32 &\Rightarrow& \I32X4.\VABS \\ &&|&
@@ -758,7 +758,7 @@ All other SIMD instructions are plain opcodes without any immediates.
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.. math::
760760
\begin{array}{llclll}
761-
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
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\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
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\hex{FD}~~192{:}\Bu32 &\Rightarrow& \I64X2.\VABS \\ &&|&
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\hex{FD}~~193{:}\Bu32 &\Rightarrow& \I64X2.\VNEG \\ &&|&
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\hex{FD}~~195{:}\Bu32 &\Rightarrow& \I64X2.\ALLTRUE \\ &&|&
@@ -784,7 +784,7 @@ All other SIMD instructions are plain opcodes without any immediates.
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785785
.. math::
786786
\begin{array}{llclll}
787-
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
787+
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
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\hex{FD}~~103{:}\Bu32 &\Rightarrow& \F32X4.\VCEIL \\ &&|&
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\hex{FD}~~104{:}\Bu32 &\Rightarrow& \F32X4.\VFLOOR \\ &&|&
790790
\hex{FD}~~105{:}\Bu32 &\Rightarrow& \F32X4.\VTRUNC \\ &&|&
@@ -804,7 +804,7 @@ All other SIMD instructions are plain opcodes without any immediates.
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805805
.. math::
806806
\begin{array}{llclll}
807-
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
807+
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
808808
\hex{FD}~~116{:}\Bu32 &\Rightarrow& \F64X2.\VCEIL \\ &&|&
809809
\hex{FD}~~117{:}\Bu32 &\Rightarrow& \F64X2.\VFLOOR \\ &&|&
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\hex{FD}~~122{:}\Bu32 &\Rightarrow& \F64X2.\VTRUNC \\ &&|&
@@ -824,7 +824,7 @@ All other SIMD instructions are plain opcodes without any immediates.
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825825
.. math::
826826
\begin{array}{llclll}
827-
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
827+
\phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{vechaslongerinstructionnames} \\[-2ex] &&|&
828828
\hex{FD}~~248{:}\Bu32 &\Rightarrow& \I32X4.\TRUNC\K{\_sat\_f32x4\_s} \\ &&|&
829829
\hex{FD}~~249{:}\Bu32 &\Rightarrow& \I32X4.\TRUNC\K{\_sat\_f32x4\_u} \\ &&|&
830830
\hex{FD}~~250{:}\Bu32 &\Rightarrow& \F32X4.\CONVERT\K{\_i32x4\_s} \\ &&|&

‎document/core/binary/types.rst

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@@ -25,7 +25,22 @@ Number Types
2525
\hex{7F} &\Rightarrow& \I32 \\ &&|&
2626
\hex{7E} &\Rightarrow& \I64 \\ &&|&
2727
\hex{7D} &\Rightarrow& \F32 \\ &&|&
28-
\hex{7C} &\Rightarrow& \F64 \\ &&|&
28+
\hex{7C} &\Rightarrow& \F64 \\
29+
\end{array}
30+
31+
32+
.. index:: vector type
33+
pair: binary format; vector type
34+
.. _binary-vectype:
35+
36+
Vector Types
37+
~~~~~~~~~~~~
38+
39+
:ref:`Vector types <syntax-vectype>` are also encoded by a single byte.
40+
41+
.. math::
42+
\begin{array}{llclll@{\qquad\qquad}l}
43+
\production{vector type} & \Bvectype &::=&
2944
\hex{7B} &\Rightarrow& \V128 \\
3045
\end{array}
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