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5 files changed +3
-4
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[submodule "third_party/silabs/wifi_sdk "]
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path = third_party/silabs/wifi_sdk
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url = https://github.com/SiliconLabs/wiseconnect.git
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- branch = v3.3.2
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+ branch = v3.3.3
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platforms = silabs
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[submodule "editline "]
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path = third_party/editline/repo
Original file line number Diff line number Diff line change @@ -38,7 +38,6 @@ extern "C" {
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#include " rsi_board.h"
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#include " rsi_debug.h"
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#include " rsi_rom_egpio.h"
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- #include " sl_si91x_usart.h"
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#else // For EFR32
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#if (_SILICON_LABS_32B_SERIES < 3)
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#include " em_core.h"
Original file line number Diff line number Diff line change @@ -38,6 +38,7 @@ extern "C" {
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#include " sl_si91x_button_pin_config.h"
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#include " sl_si91x_led.h"
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#include " sl_si91x_led_config.h"
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+ #include " sl_si91x_led_instances.h"
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#if CHIP_CONFIG_ENABLE_ICD_SERVER == 0
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void soc_pll_config (void );
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//! Scan types
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#define SCAN_TYPE_ACTIVE (0x01)
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- #define SCAN_TYPE_PASSIVE (0x00)
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//! Scan filters
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#define SCAN_FILTER_TYPE_ALL (0x00)
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