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Test failure: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_GatherVectorFirstFaulting_Bases_double_ulong() #114646

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BruceForstall opened this issue Apr 14, 2025 · 4 comments
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arch-arm64 area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI blocking-clean-ci-optional Blocking optional rolling runs JitStress CLR JIT issues involving JIT internal stress modes
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@BruceForstall
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pipeline: runtime-coreclr r2r-extra
job: R2R-CG2 windows arm64 Checked jitstress1_tiered @ Windows.11.Arm64.Open
test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_GatherVectorFirstFaulting_Bases_double_ulong()

https://dev.azure.com/dnceng-public/public/_build/results?buildId=1015023&view=ms.vss-test-web.build-test-results-tab

set DOTNET_TieredCompilation=1
set DOTNET_JitStress=1
04:01:40.246 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_GatherVectorFirstFaulting_Bases_double_ulong()
Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunBasicScenario_Load
Beginning scenario: RunBasicScenario_LoadFirstFaulting
Sve.GatherVectorFirstFaulting<Double>(Double, UInt64): RunBasicScenario_LoadFirstFaulting failed:
       firstOp: (1, 1)
      secondOp: (2787062738098, 0)
        result: (NaN, 0)
   faultResult: (<1, 0>)

Beginning scenario: RunBasicScenario_FalseMask
Beginning scenario: RunBasicScenario_NonFaulting
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
Beginning scenario: ConditionalSelect_FalseOp_mask - operation in TrueValue
Beginning scenario: ConditionalSelect_FalseOp_zero - operation in TrueValue
Beginning scenario: ConditionalSelect_FalseOp_all - operation in TrueValue
Beginning scenario: ConditionalSelect_FalseOp_mask - operation in FalseValue
Beginning scenario: ConditionalSelect_FalseOp_zero - operation in FalseValue
Beginning scenario: ConditionalSelect_FalseOp_all - operation in FalseValue
Beginning scenario: ConditionalSelect_ZeroOp_mask - operation in TrueValue
Beginning scenario: ConditionalSelect_ZeroOp_zero - operation in TrueValue
Beginning scenario: ConditionalSelect_ZeroOp_all - operation in TrueValue
Beginning scenario: ConditionalSelect_ZeroOp_mask - operation in FalseValue
Beginning scenario: ConditionalSelect_ZeroOp_zero - operation in FalseValue
Beginning scenario: ConditionalSelect_ZeroOp_all - operation in FalseValue
System.Exception: One or more scenarios did not complete as expected.
   at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_GatherVectorFirstFaulting_Bases_double_ulong() in /__w/1/s/artifacts/tests/coreclr/obj/AnyOS.x64.Checked/Managed/JIT/HardwareIntrinsics/Arm/Sve/Sve_r/Sve_r/gen/Sve.GatherVectorFirstFaulting.Bases.double.ulong.cs:line 76
   at Program.<<Main>$>g__TestExecutor3205|0_3206(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&)
04:01:40.920 Failed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_GatherVectorFirstFaulting_Bases_double_ulong()

@dotnet/jit-contrib @dotnet/arm64-contrib

@BruceForstall BruceForstall added arch-arm64 blocking-clean-ci-optional Blocking optional rolling runs JitStress CLR JIT issues involving JIT internal stress modes labels Apr 14, 2025
@BruceForstall BruceForstall added this to the 10.0.0 milestone Apr 14, 2025
@dotnet-issue-labeler dotnet-issue-labeler bot added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Apr 14, 2025
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

@BruceForstall
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Related to #112264?

@SakeTao
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SakeTao commented Apr 15, 2025

Failed in: runtime-coreclr r2r-extra 20250413.1

Failed tests:

R2R-CG2 windows arm64 Checked jitstress1_tiered @ Windows.11.Arm64.Open
    - _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_GatherVectorFirstFaulting_Bases_double_ulong()

Error message:

 One or more scenarios did not complete as expected.

Stack trace:

   at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_GatherVectorFirstFaulting_Bases_double_ulong() in /__w/1/s/artifacts/tests/coreclr/obj/AnyOS.x64.Checked/Managed/JIT/HardwareIntrinsics/Arm/Sve/Sve_r/Sve_r/gen/Sve.GatherVectorFirstFaulting.Bases.double.ulong.cs:line 76
   at Program.<<Main>$>g__TestExecutor3205|0_3206(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&)

@a74nh
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a74nh commented Apr 15, 2025

Related to #112264?

Looks like the same thing.

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arch-arm64 area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI blocking-clean-ci-optional Blocking optional rolling runs JitStress CLR JIT issues involving JIT internal stress modes
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