x86: pass through cpuid leaves 15h and 16h

These leaves communicate TSC and CPU frequencies to the guest, and
are used by the guest as a preferred means of calibration. This is
especially important in secret-free contexts, where kvm-clock is not
available (so guest cannot get TSC frequency from there), and
calibration against PIT is unreliable.

Signed-off-by: Patrick Roy <roypat@amazon.co.uk>

Author: roypat

CHANGELOG.md

@@ -21,6 +21,9 @@ and this project adheres to
   so users need to regenerate snapshots.
 - [#4731](https://github.com/firecracker-microvm/firecracker/pull/4731): Added
   support for modifying the host TAP device name during snapshot restore.
+- [#5186](https://github.com/firecracker-microvm/firecracker/pull/5186): Pass
+  through CPUID leaves 15h and 16h on Intel CPUs (Crystal clock, processor, and
+  and bus frequencies).
 
 ### Changed
 

src/vmm/src/cpu_config/x86_64/cpuid/intel/normalize.rs

@@ -5,7 +5,7 @@ use crate::cpu_config::x86_64::cpuid::normalize::{
     CheckedAssignError, get_range, set_bit, set_range,
 };
 use crate::cpu_config::x86_64::cpuid::{
-    BRAND_STRING_LENGTH, CpuidKey, CpuidRegisters, CpuidTrait, MissingBrandStringLeaves,
+    BRAND_STRING_LENGTH, CpuidKey, CpuidRegisters, CpuidTrait, MissingBrandStringLeaves, cpuid,
     host_brand_string,
 };
 
@@ -71,10 +71,53 @@ impl super::IntelCpuid {
         self.update_performance_monitoring_entry()?;
         self.update_extended_topology_v2_entry();
         self.update_brand_string_entry()?;
+        self.update_frequency_information();
 
         Ok(())
     }
 
+    /// Passes through the host value of cpuid leaves 15h and 16h if they
+    /// are not already configured via cpu template.
+    fn update_frequency_information(&mut self) {
+        let Some(leaf_15h) = self.get_mut(&CpuidKey::leaf(0x15)) else {
+            return;
+        };
+
+        if leaf_15h.result == CpuidRegisters::default() {
+            let host_leaf_15 = cpuid(0x15);
+
+            // CPUID.15H:EAX[31:0]
+            // Ratio of TSC frequency to Core Crystal Clock frequency, denominator
+            leaf_15h.result.eax = host_leaf_15.eax;
+            // CPUID.15H:EBX[31:0]
+            // Ratio of TSC frequency to Core Crystal Clock frequency, numerator
+            leaf_15h.result.ebx = host_leaf_15.ebx;
+            // CPUID.15H:ECX[31:0]
+            // Core Crystal Clock frequency, in units of Hz
+            leaf_15h.result.ecx = host_leaf_15.ecx;
+            // edx is reserved
+        }
+
+        let Some(leaf_16h) = self.get_mut(&CpuidKey::leaf(0x16)) else {
+            return;
+        };
+
+        if leaf_16h.result == CpuidRegisters::default() {
+            let host_leaf_16 = cpuid(0x16);
+
+            // CPUID.16H:EAX[15:0]
+            // Processor Base Frequency (in MHz)
+            leaf_16h.result.eax = host_leaf_16.eax;
+            // CPUID.16H:EBX[15:0]
+            // Processor Maximum Frequency (in MHz)
+            leaf_16h.result.ebx = host_leaf_16.ebx;
+            // CPUID.16H:ECX[15:0]
+            // Bus/Reference frequency (in MHz)
+            leaf_16h.result.ecx = host_leaf_16.ecx;
+            // edx is reserved
+        }
+    }
+
     /// Update deterministic cache entry
     #[allow(clippy::unwrap_in_result)]
     fn update_deterministic_cache_entry(