[nrf fromlist] boards: nordic: Add nRF54L09 FLPR

Add nrF54L09 FLPR core support.

Upstream PR #: 85310

Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>

Author: adamkondraciuk

boards/nordic/nrf54l09pdk/Kconfig.nrf54l09pdk

@@ -3,3 +3,4 @@
 
 config BOARD_NRF54L09PDK
 	select SOC_NRF54L09_ENGA_CPUAPP if BOARD_NRF54L09PDK_NRF54L09_CPUAPP
+	select SOC_NRF54L09_ENGA_CPUFLPR if BOARD_NRF54L09PDK_NRF54L09_CPUFLPR

boards/nordic/nrf54l09pdk/board.cmake

@@ -1,7 +1,11 @@
 # Copyright (c) 2024 Nordic Semiconductor ASA
 # SPDX-License-Identifier: Apache-2.0
 
-board_runner_args(jlink "--device=cortex-m33" "--speed=4000")
+if(CONFIG_BOARD_NRF54L09PDK_NRF54L09_CPUAPP)
+  board_runner_args(jlink "--device=cortex-m33" "--speed=4000")
+elseif(CONFIG_BOARD_NRF54L09PDK_NRF54L09_CPUFLPR)
+  board_runner_args(jlink "--speed=4000")
+endif()
 
 include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09-common.dtsi

@@ -60,3 +60,15 @@
 	pinctrl-1 = <&uart20_sleep>;
 	pinctrl-names = "default", "sleep";
 };
+
+&uart30 {
+	current-speed = <115200>;
+	pinctrl-0 = <&uart30_default>;
+	pinctrl-1 = <&uart30_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&hfpll {
+	/* For now use 64 MHz clock for CPU and fast peripherals. */
+	clock-frequency = <DT_FREQ_M(64)>;
+};

boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09-pinctrl.dtsi

@@ -21,4 +21,27 @@
 			low-power-enable;
 		};
 	};
+
+	/omit-if-no-ref/ uart30_default: uart30_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 0, 0)>,
+				<NRF_PSEL(UART_RTS, 0, 2)>;
+		};
+
+		group2 {
+			psels = <NRF_PSEL(UART_RX, 0, 1)>,
+				<NRF_PSEL(UART_CTS, 0, 3)>;
+			bias-pull-up;
+		};
+	};
+
+	/omit-if-no-ref/ uart30_sleep: uart30_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 0, 0)>,
+				<NRF_PSEL(UART_RX, 0, 1)>,
+				<NRF_PSEL(UART_RTS, 0, 2)>,
+				<NRF_PSEL(UART_CTS, 0, 3)>;
+			low-power-enable;
+		};
+	};
 };

boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuflpr.dts

@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <nordic/nrf54l09_enga_cpuflpr.dtsi>
+#include "nrf54l09pdk_nrf54l09-common.dtsi"
+
+/ {
+	model = "Nordic nRF54L09 PDK nRF54L09 FLPR MCU";
+	compatible = "nordic,nrf54l09pdk_nrf54l09-cpuflpr";
+
+	chosen {
+		zephyr,console = &uart30;
+		zephyr,shell-uart = &uart30;
+		zephyr,code-partition = &cpuflpr_code_partition;
+		zephyr,flash = &cpuflpr_rram;
+		zephyr,sram = &cpuflpr_sram;
+	};
+};
+
+&cpuflpr_sram {
+	status = "okay";
+};
+
+&cpuflpr_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		cpuflpr_code_partition: partition@0 {
+			label = "image-0";
+			reg = <0x0 DT_SIZE_K(48)>;
+		};
+	};
+};
+
+&grtc {
+	owned-channels = <3 4>;
+	status = "okay";
+};
+
+&uart30 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpiote20 {
+	status = "okay";
+};
+
+&gpiote30 {
+	status = "okay";
+};

boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuflpr.yaml

@@ -0,0 +1,15 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: nrf54l09pdk/nrf54l09/cpuflpr
+name: nRF54L09-PDK-nRF54L09-Fast-Lightweight-Peripheral-Processor
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+sysbuild: true
+ram: 48
+flash: 48
+supported:
+  - counter
+  - gpio

boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuflpr_defconfig

@@ -0,0 +1,17 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+CONFIG_USE_DT_CODE_PARTITION=y
+
+# Execute from SRAM
+CONFIG_XIP=n