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| 1 | +/* |
| 2 | + * Copyright (c) 2023, 2024, Oracle and/or its affiliates. All rights reserved. |
| 3 | + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 | + * |
| 5 | + * This code is free software; you can redistribute it and/or modify it |
| 6 | + * under the terms of the GNU General Public License version 2 only, as |
| 7 | + * published by the Free Software Foundation. Oracle designates this |
| 8 | + * particular file as subject to the "Classpath" exception as provided |
| 9 | + * by Oracle in the LICENSE file that accompanied this code. |
| 10 | + * |
| 11 | + * This code is distributed in the hope that it will be useful, but WITHOUT |
| 12 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 14 | + * version 2 for more details (a copy is included in the LICENSE file that |
| 15 | + * accompanied this code). |
| 16 | + * |
| 17 | + * You should have received a copy of the GNU General Public License version |
| 18 | + * 2 along with this work; if not, write to the Free Software Foundation, |
| 19 | + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
| 20 | + * |
| 21 | + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
| 22 | + * or visit www.oracle.com if you need additional information or have any |
| 23 | + * questions. |
| 24 | + */ |
| 25 | +package org.graalvm.compiler.core.amd64; |
| 26 | + |
| 27 | +import jdk.vm.ci.amd64.AMD64; |
| 28 | +import jdk.vm.ci.amd64.AMD64Kind; |
| 29 | +import jdk.vm.ci.code.RegisterValue; |
| 30 | +import jdk.vm.ci.code.ValueUtil; |
| 31 | +import jdk.vm.ci.meta.AllocatableValue; |
| 32 | +import jdk.vm.ci.meta.Value; |
| 33 | +import org.graalvm.compiler.asm.amd64.AMD64MacroAssembler; |
| 34 | +import org.graalvm.compiler.core.common.LIRKind; |
| 35 | +import org.graalvm.compiler.lir.LIRInstructionClass; |
| 36 | +import org.graalvm.compiler.lir.Opcode; |
| 37 | +import org.graalvm.compiler.lir.amd64.AMD64LIRInstruction; |
| 38 | +import org.graalvm.compiler.lir.asm.CompilationResultBuilder; |
| 39 | + |
| 40 | +import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.REG; |
| 41 | + |
| 42 | +/** |
| 43 | + * Writes the value of EAX into PKRU. ECX and EDX must be 0 when WRPKRU is executed; otherwise, a |
| 44 | + * general protection exception (#GP) occurs. WRPKRU can be executed only if CR4.PKE = 1; otherwise, |
| 45 | + * an invalid-opcode exception (#UD) occurs. Software can discover the value of CR4.PKE by examining |
| 46 | + * CPUID.(EAX=07H,ECX=0H):ECX.OSPKE [bit 4]. On processors that support the Intel 64 Architecture, |
| 47 | + * the high-order 32-bits of RCX, RDX and RAX are ignored. |
| 48 | + */ |
| 49 | +@Opcode("WRPKRU") |
| 50 | +public class AMD64WriteDataToUserPageKeyRegister extends AMD64LIRInstruction { |
| 51 | + public static final LIRInstructionClass<AMD64WriteDataToUserPageKeyRegister> TYPE = LIRInstructionClass.create(AMD64WriteDataToUserPageKeyRegister.class); |
| 52 | + |
| 53 | + // the argument to wrpkru is in eax |
| 54 | + @Use protected Value arg; |
| 55 | + // ecx and edx need to be zero |
| 56 | + @Temp({REG}) protected AllocatableValue zeroArg1; |
| 57 | + @Temp({REG}) protected AllocatableValue zeroArg2; |
| 58 | + |
| 59 | + public AMD64WriteDataToUserPageKeyRegister(RegisterValue arg) { |
| 60 | + super(TYPE); |
| 61 | + assert arg.getRegister().equals(AMD64.rax); |
| 62 | + this.arg = arg; |
| 63 | + zeroArg1 = AMD64.rcx.asValue(LIRKind.value(AMD64Kind.DWORD)); |
| 64 | + zeroArg2 = AMD64.rdx.asValue(LIRKind.value(AMD64Kind.DWORD)); |
| 65 | + } |
| 66 | + |
| 67 | + @Override |
| 68 | + public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) { |
| 69 | + masm.xorl(ValueUtil.asRegister(zeroArg1), ValueUtil.asRegister(zeroArg1)); |
| 70 | + masm.xorl(ValueUtil.asRegister(zeroArg2), ValueUtil.asRegister(zeroArg2)); |
| 71 | + masm.wrpkru(); |
| 72 | + } |
| 73 | +} |
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