RX580 warning, writing pp table back crashes driver

[hpvb]

When I run sudo ./amdtweak --card 0 --read-card-pp --print the first line printed is WARNING: 'HardLimitTable': Couldn't find versioned type 'HardLimitTable$1'

When trying to make what I think of as a safe like this:
sudo ./amdtweak --card 0 --read-card-pp --set FanTable.TargetTemperature=70 --write-card-pp

The amdgpu driver either just completely stops functioning or prints a kernel panic before locking up the machine.

As for what I'm trying to achieve: I'm trying to undervolt my card to see if I can improve the thermals a little bit.

WARNING: 'HardLimitTable': Couldn't find versioned type 'HardLimitTable$1'
Card '0': {
  "StructureSize": 848,
  "TableFormatRevision": 7,
  "TableContentRevision": 1,
  "RevisionId": 0,
  "TableSize": 77,
  "GoldenPPId": 1699,
  "GoldenRevision": 10388,
  "FormatId": 25,
  "VoltageTime": 0,
  "PlatformCaps": 33587202,
  "SocClockMaxOD": 0,
  "MemClockMaxOD": 0,
  "PowerControlLimit": 50,
  "UlvVoltageOffset": 50,
  "StateTable": {
    "RevisionId": 1,
    "NumEntries": 3,
    "Entries": [
      {
        "SocClockIndexHigh": 0,
        "SocClockIndexLow": 0,
        "MemClockIndexHigh": 0,
        "MemClockIndexLow": 0,
        "PCIEGenLow": 0,
        "PCIEGenHigh": 0,
        "PCIELaneLow": 0,
        "PCIELaneHigh": 0,
        "Classification": 8,
        "CapsAndSettings": 0,
        "Classification2": 0,
        "Reserved1": 0
      },
      {
        "SocClockIndexHigh": 3,
        "SocClockIndexLow": 0,
        "MemClockIndexHigh": 1,
        "MemClockIndexLow": 0,
        "PCIEGenLow": 0,
        "PCIEGenHigh": 0,
        "PCIELaneLow": 0,
        "PCIELaneHigh": 0,
        "Classification": 5,
        "CapsAndSettings": 16384,
        "Classification2": 0,
        "Reserved1": 0
      },
      {
        "SocClockIndexHigh": 1,
        "SocClockIndexLow": 0,
        "MemClockIndexHigh": 0,
        "MemClockIndexLow": 0,
        "PCIEGenLow": 0,
        "PCIEGenHigh": 0,
        "PCIELaneLow": 0,
        "PCIELaneHigh": 0,
        "Classification": 1,
        "CapsAndSettings": 0,
        "Classification2": 1,
        "Reserved1": 0
      }
    ]
  },
  "FanTable": {
    "RevisionId": 9,
    "THyst": 3,
    "TMin": 4000,
    "TMed": 6500,
    "THigh": 8500,
    "PWMMin": 2000,
    "PWMMed": 4000,
    "PWMHigh": 6000,
    "TMax": 10900,
    "FanControlMode": 1,
    "FanPWMMax": 100,
    "FanOutputSensitivity": 4836,
    "FanRPMMax": 2200,
    "MinFanSocClockAcousticLimit": 91000,
    "TargetTemperature": 80,
    "MinimumPWMLimit": 20,
    "Reserved1": 100
  },
  "ThermalController": {
    "RevisionId": 1,
    "ControlType": 23,
    "I2CLine": 0,
    "I2CAddress": 0,
    "FanParameters": 128,
    "FanMinRPM": 0,
    "FanMaxRPM": 0,
    "Reserved1": 0,
    "Flags": 0
  },
  "Reserved1": 0,
  "MemClockDependencyTable": {
    "RevisionId": 0,
    "NumEntries": 2,
    "Entries": [
      {
        "Vddc": 0,
        "Vddci": 850,
        "VddcGfxOffset": 0,
        "Mvdd": 1000,
        "MemClock": 30000,
        "Reserved1": 0
      },
      {
        "Vddc": 11,
        "Vddci": 950,
        "VddcGfxOffset": 0,
        "Mvdd": 1000,
        "MemClock": 200000,
        "Reserved1": 0
      }
    ]
  },
  "SocClockDependencyTable": {
    "RevisionId": 1,
    "NumEntries": 8,
    "Entries": [
      {
        "Vddc": 0,
        "VddcOffset": 0,
        "SocClock": 30000,
        "EDCCurrent": 0,
        "ReliabilityTemperature": 0,
        "CKSOffsetAndDisable": 128,
        "SocClockOffset": 0
      },
      {
        "Vddc": 1,
        "VddcOffset": -26,
        "SocClock": 60800,
        "EDCCurrent": 0,
        "ReliabilityTemperature": 0,
        "CKSOffsetAndDisable": 0,
        "SocClockOffset": 0
      },
      {
        "Vddc": 2,
        "VddcOffset": -26,
        "SocClock": 91000,
        "EDCCurrent": 0,
        "ReliabilityTemperature": 0,
        "CKSOffsetAndDisable": 0,
        "SocClockOffset": 5000
      },
      {
        "Vddc": 3,
        "VddcOffset": -26,
        "SocClock": 107700,
        "EDCCurrent": 0,
        "ReliabilityTemperature": 0,
        "CKSOffsetAndDisable": 0,
        "SocClockOffset": 0
      },
      {
        "Vddc": 4,
        "VddcOffset": -26,
        "SocClock": 107700,
        "EDCCurrent": 0,
        "ReliabilityTemperature": 0,
        "CKSOffsetAndDisable": 0,
        "SocClockOffset": 0
      },
      {
        "Vddc": 5,
        "VddcOffset": -26,
        "SocClock": 107700,
        "EDCCurrent": 0,
        "ReliabilityTemperature": 0,
        "CKSOffsetAndDisable": 0,
        "SocClockOffset": 0
      },
      {
        "Vddc": 6,
        "VddcOffset": -26,
        "SocClock": 107700,
        "EDCCurrent": 0,
        "ReliabilityTemperature": 0,
        "CKSOffsetAndDisable": 0,
        "SocClockOffset": 0
      },
      {
        "Vddc": 7,
        "VddcOffset": 0,
        "SocClock": 107700,
        "EDCCurrent": 0,
        "ReliabilityTemperature": 0,
        "CKSOffsetAndDisable": 0,
        "SocClockOffset": 0
      }
    ]
  },
  "VddcLookupTable": {
    "RevisionId": 0,
    "NumEntries": 15,
    "Entries": [
      {
        "Vdd": 800,
        "CACLow": 0,
        "CACMid": 0,
        "CACHigh": 0
      },
      {
        "Vdd": 65282,
        "CACLow": 0,
        "CACMid": 0,
        "CACHigh": 0
      },
      {
        "Vdd": 65283,
        "CACLow": 0,
        "CACMid": 0,
        "CACHigh": 0
      },
      {
        "Vdd": 65284,
        "CACLow": 0,
        "CACMid": 0,
        "CACHigh": 0
      },
      {
        "Vdd": 65285,
        "CACLow": 0,
        "CACMid": 0,
        "CACHigh": 0
      },
      {
        "Vdd": 65286,
        "CACLow": 0,
        "CACMid": 0,
        "CACHigh": 0
      },
      {
        "Vdd": 65287,
        "CACLow": 0,
        "CACMid": 0,
        "CACHigh": 0
      },
      {
        "Vdd": 65288,
        "CACLow": 0,
        "CACMid": 0,
        "CACHigh": 0
      },
      {
        "Vdd": 850,
        "CACLow": 0,
        "CACMid": 0,
        "CACHigh": 0
      },
      {
        "Vdd": 900,
        "CACLow": 0,
        "CACMid": 0,
        "CACHigh": 0
      },
      {
        "Vdd": 950,
        "CACLow": 0,
        "CACMid": 0,
        "CACHigh": 0
      },
      {
        "Vdd": 1000,
        "CACLow": 0,
        "CACMid": 0,
        "CACHigh": 0
      },
      {
        "Vdd": 1050,
        "CACLow": 0,
        "CACMid": 0,
        "CACHigh": 0
      },
      {
        "Vdd": 1100,
        "CACLow": 0,
        "CACMid": 0,
        "CACHigh": 0
      },
      {
        "Vdd": 1150,
        "CACLow": 0,
        "CACMid": 0,
        "CACHigh": 0
      }
    ]
  },
  "VddGfxLookupTable": {
    "RevisionId": 0,
    "NumEntries": 8,
    "Entries": [
      {
        "Vdd": 900,
        "CACLow": 0,
        "CACMid": 0,
        "CACHigh": 0
      },
      {
        "Vdd": 65282,
        "CACLow": 0,
        "CACMid": 0,
        "CACHigh": 0
      },
      {
        "Vdd": 65283,
        "CACLow": 0,
        "CACMid": 0,
        "CACHigh": 0
      },
      {
        "Vdd": 65284,
        "CACLow": 0,
        "CACMid": 0,
        "CACHigh": 0
      },
      {
        "Vdd": 65285,
        "CACLow": 0,
        "CACMid": 0,
        "CACHigh": 0
      },
      {
        "Vdd": 65286,
        "CACLow": 0,
        "CACMid": 0,
        "CACHigh": 0
      },
      {
        "Vdd": 65287,
        "CACLow": 0,
        "CACMid": 0,
        "CACHigh": 0
      },
      {
        "Vdd": 65288,
        "CACLow": 0,
        "CACMid": 0,
        "CACHigh": 0
      }
    ]
  },
  "MMDependencyTable": {
    "RevisionId": 0,
    "NumEntries": 8,
    "Entries": [
      {
        "Vddc": 0,
        "VddcGfxOffset": 0,
        "DCLK": 58000,
        "VCLK": 75000,
        "ECLK": 63000,
        "ACLK": 0,
        "SAMUCLK": 57000
      },
      {
        "Vddc": 8,
        "VddcGfxOffset": -76,
        "DCLK": 63000,
        "VCLK": 80000,
        "ECLK": 69000,
        "ACLK": 0,
        "SAMUCLK": 64000
      },
      {
        "Vddc": 9,
        "VddcGfxOffset": -101,
        "DCLK": 68000,
        "VCLK": 85000,
        "ECLK": 75000,
        "ACLK": 0,
        "SAMUCLK": 70000
      },
      {
        "Vddc": 10,
        "VddcGfxOffset": -126,
        "DCLK": 73000,
        "VCLK": 89000,
        "ECLK": 81000,
        "ACLK": 0,
        "SAMUCLK": 76000
      },
      {
        "Vddc": 11,
        "VddcGfxOffset": -151,
        "DCLK": 77000,
        "VCLK": 92000,
        "ECLK": 86000,
        "ACLK": 0,
        "SAMUCLK": 81000
      },
      {
        "Vddc": 12,
        "VddcGfxOffset": -201,
        "DCLK": 80000,
        "VCLK": 95000,
        "ECLK": 91000,
        "ACLK": 0,
        "SAMUCLK": 85000
      },
      {
        "Vddc": 13,
        "VddcGfxOffset": -251,
        "DCLK": 83000,
        "VCLK": 98000,
        "ECLK": 96000,
        "ACLK": 0,
        "SAMUCLK": 88000
      },
      {
        "Vddc": 14,
        "VddcGfxOffset": 0,
        "DCLK": 86000,
        "VCLK": 100000,
        "ECLK": 100000,
        "ACLK": 0,
        "SAMUCLK": 91000
      }
    ]
  },
  "VCEStateTable": {
    "RevisionId": 1,
    "NumEntries": 6,
    "Entries": [
      {
        "VCEClockIndex": 0,
        "Flag": 0,
        "SocClockIndex": 1,
        "MemClockIndex": 1
      },
      {
        "VCEClockIndex": 0,
        "Flag": 1,
        "SocClockIndex": 1,
        "MemClockIndex": 1
      },
      {
        "VCEClockIndex": 0,
        "Flag": 2,
        "SocClockIndex": 1,
        "MemClockIndex": 1
      },
      {
        "VCEClockIndex": 0,
        "Flag": 2,
        "SocClockIndex": 1,
        "MemClockIndex": 1
      },
      {
        "VCEClockIndex": 0,
        "Flag": 2,
        "SocClockIndex": 1,
        "MemClockIndex": 1
      },
      {
        "VCEClockIndex": 0,
        "Flag": 2,
        "SocClockIndex": 1,
        "MemClockIndex": 1
      }
    ]
  },
  "PPMTable": null,
  "PowerTuneTable": {
    "RevisionId": 4,
    "TDP": 68,
    "ConfigurableTDP": 0,
    "TDC": 74,
    "BatteryPowerLimit": 65,
    "SmallPowerLimit": 65,
    "LowCACLeakage": 0,
    "HighCACLeakage": 0,
    "MaximumPowerDeliveryLimit": 68,
    "TjMax": 92,
    "PowerTuneDataSetId": 0,
    "EDCLimit": 0,
    "SoftwareShutdownTemp": 94,
    "ClockStretchAmount": 2,
    "TemperatureLimitHotspot": 105,
    "TemperatureLimitLiquid1": 80,
    "TemperatureLimitLiquid2": 80,
    "TemperatureLimitVrVddc": 115,
    "TemperatureLimitVrMvdd": 115,
    "TemperatureLimitPlx": 95,
    "Liquid1I2CAddress": 0,
    "Liquid2I2CAddress": 0,
    "LiquidI2CLine": 144,
    "VrI2CAddress": 16,
    "VrI2CLine": 150,
    "PlxI2CAddress": 0,
    "PlxI2CLine": 144,
    "Reserved1": 0
  },
  "HardLimitTable": {
    "RevisionId": 1,
    "NumEntries": 1
  },
  "PCIETable": {
    "RevisionId": 1,
    "NumEntries": 3,
    "Entries": [
      {
        "PCIEGenSpeed": 2,
        "PCIELaneWidth": 16,
        "Reserved1": 0,
        "PCIEClock": 0
      },
      {
        "PCIEGenSpeed": 2,
        "PCIELaneWidth": 16,
        "Reserved1": 0,
        "PCIEClock": 0
      },
      {
        "PCIEGenSpeed": 2,
        "PCIELaneWidth": 16,
        "Reserved1": 0,
        "PCIEClock": 0
      }
    ]
  },
  "GPIOTable": {
    "RevisionId": 0,
    "VRHotTriggeredSocClockDPMIndex": 1,
    "Reserved1": 0,
    "Reserved2": 0,
    "Reserved3": 0,
    "Reserved4": 0,
    "Reserved5": 0
  },
  "Reserved2": 62564,
  "Reserved3": 1,
  "Reserved4": 1875,
  "Reserved5": 0,
  "Reserved6": 0,
  "Reserved7": 0
}

[kobalicek]

Hello, I would need your pp_table to test it locally (and add it to tests). There were historically some bugs in read/write so it's possible the table gets corrupted.

[hpvb]

Sure thing! https://tmm.cx/~hp/pp_table

[kobalicek]

Thanks man! I have updated the repo with this one, but it seems it's read/written properly (I mean no deserialization and serialization issue). Can you try to just cat the table from the driver and then to store the same table there again (without using amdtweak)? If the driver crashes this way then it's a bug and should be reported to AMD. Otherwise amdtweak is doing something wrong

[hpvb]

Just writing pp_table to a file and pushing it back doesn't cause a crash just a short monitor flickering.

[hpvb]

For your test: This pp_table is from an Asus GL702ZC laptop which has some peculiar speed restrictions and voltages. I don't know how representative it is of a 'regular' RX580 pp_table. You may want to explicitly name it so when you get your hands on a 'normal' RX580 pp_table file you can test both.

[Lucie2A]

Fixed : Polaris hard limit record is same as Tonga but with version number '1' (Tonga seams to have v '52')
This patch has not been pushed/commit to master yet, but you can fix the code yourself (vbios.js, line ~3000+).

// ATOM Polaris Hard Limit Record - Retro Engineering from a laptop Polaris Bios pp_table
vbios.$define({
  $name: "HardLimitEntry",
  $version: [1],
  $members: [
    { $name: "SocClockLimit"                  , $type: U32 },
    { $name: "MemClockLimit"                  , $type: U32 },
    { $name: "VddcLimit"                      , $type: U16 },
    { $name: "VddciLimit"                     , $type: U16 },
    { $name: "VddGfxLimit"                    , $type: U16 }
  ]
});
.../...
vbios.$define({
  $extend: vbios.HardLimitTable,
  $version: [1],
  $members: [
    { $name: "Entries"                        , $type: Arr, $ref: vbios.HardLimitEntry$1, $length: "NumEntries" }
  ]
});

  "HardLimitTable": {
    "RevisionId": 1,
    "NumEntries": 1,
    "Entries": [
      {
        "SocClockLimit": 30000,
        "MemClockLimit": 30000,
        "VddcLimit": 1000,
        "VddciLimit": 1000,
        "VddGfxLimit": 1000
      }
    ]
  },