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core: update to newer interrupt code, seems to affect timings too
pcsxr-svn commit: Author: weimingzhi Date: Sat Aug 7 23:52:44 2010 +0000 refactored the interrupt scheduling code a bit to make it a little more readable than using those "magic" numbers.
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-84
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12 files changed

+112
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‎ChangeLog

+14
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,17 @@
1+
August 7, 2010 Wei Mingzhi <whistler_wmz@users.sf.net>
2+
3+
* libpcsxcore/r3000a.h: Refactored the interrupt scheduling code to make it a
4+
little more readable than using the "magic" numbers.
5+
* libpcsxcore/r3000a.c: Likewise.
6+
* libpcsxcore/cdrom.c: Likewise.
7+
* libpcsxcore/mdec.c: Likewise.
8+
* libpcsxcore/sio.c: Likewise.
9+
* libpcsxcore/psxdma.h: Likewise.
10+
* libpcsxcore/misc.c: Bumped savestate version.
11+
* debian/changelog: Updated version.
12+
* macosx/Info.plist: Likewise.
13+
* po/zh_TW.po: Corrected a minor translation error.
14+
115
August 2, 2010 Wei Mingzhi <whistler_wmz@users.sf.net>
216

317
* macosx/Pcsx.xcodeproj/project.pbxproj: Added some more optimizations

‎libpcsxcore/cdrom.c

+9-9
Original file line numberDiff line numberDiff line change
@@ -92,17 +92,17 @@ static struct CdrStat stat;
9292
static struct SubQ *subq;
9393

9494
#define CDR_INT(eCycle) { \
95-
psxRegs.interrupt |= 0x4; \
96-
psxRegs.intCycle[2 + 1] = eCycle; \
97-
psxRegs.intCycle[2] = psxRegs.cycle; \
98-
new_dyna_set_event(0, eCycle); \
95+
psxRegs.interrupt |= (1 << PSXINT_CDR); \
96+
psxRegs.intCycle[PSXINT_CDR].cycle = eCycle; \
97+
psxRegs.intCycle[PSXINT_CDR].sCycle = psxRegs.cycle; \
98+
new_dyna_set_event(PSXINT_CDR, eCycle); \
9999
}
100100

101101
#define CDREAD_INT(eCycle) { \
102-
psxRegs.interrupt |= 0x40000; \
103-
psxRegs.intCycle[2 + 16 + 1] = eCycle; \
104-
psxRegs.intCycle[2 + 16] = psxRegs.cycle; \
105-
new_dyna_set_event(2, eCycle); \
102+
psxRegs.interrupt |= (1 << PSXINT_CDREAD); \
103+
psxRegs.intCycle[PSXINT_CDREAD].cycle = eCycle; \
104+
psxRegs.intCycle[PSXINT_CDREAD].sCycle = psxRegs.cycle; \
105+
new_dyna_set_event(PSXINT_CDREAD, eCycle); \
106106
}
107107

108108
#define StartReading(type, eCycle) { \
@@ -115,7 +115,7 @@ static struct SubQ *subq;
115115
#define StopReading() { \
116116
if (cdr.Reading) { \
117117
cdr.Reading = 0; \
118-
psxRegs.interrupt &= ~0x40000; \
118+
psxRegs.interrupt &= ~(1 << PSXINT_CDREAD); \
119119
} \
120120
cdr.StatP &= ~0x20;\
121121
}

‎libpcsxcore/mdec.c

+4-5
Original file line numberDiff line numberDiff line change
@@ -543,12 +543,11 @@ void mdec1Interrupt() {
543543
if (HW_DMA1_CHCR & SWAP32(0x01000000)) {
544544
// Set a fixed value totaly arbitrarie another sound value is
545545
// PSXCLK / 60 or PSXCLK / 50 since the bug happened at end of frame.
546-
// PSXCLK / 1000 seems good for FF9. (for FF9 need < ~28000)
546+
// PSXCLK / 500 seems good for FF9.
547547
// CAUTION: commented interrupt-handling may lead to problems, keep an eye ;-)
548-
MDECOUTDMA_INT(PSXCLK / 1000 * BIAS);
549-
// psxRegs.interrupt |= 0x02000000;
550-
// psxRegs.intCycle[5 + 24 + 1] *= 8;
551-
// psxRegs.intCycle[5 + 24] = psxRegs.cycle;
548+
MDECOUTDMA_INT(PSXCLK / 500);
549+
// MDECOUTDMA_INT(psxRegs.intCycle[PSXINT_MDECOUTDMA].cycle * 8);
550+
552551
HW_DMA1_CHCR &= SWAP32(~0x01000000);
553552
DMA_INTERRUPT(1);
554553
} else {

‎libpcsxcore/misc.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -458,7 +458,7 @@ static const char PcsxHeader[32] = "STv4 PCSX v" PACKAGE_VERSION;
458458

459459
// Savestate Versioning!
460460
// If you make changes to the savestate version, please increment the value below.
461-
static const u32 SaveVersion = 0x8b410004;
461+
static const u32 SaveVersion = 0x8b410005;
462462

463463
int SaveState(const char *file) {
464464
gzFile f;

‎libpcsxcore/new_dynarec/emu_if.c

+2-1
Original file line numberDiff line numberDiff line change
@@ -12,14 +12,15 @@
1212
#include "emu_if.h"
1313
#include "pcsxmem.h"
1414
#include "../psxhle.h"
15+
#include "../r3000a.h"
1516

1617
#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
1718

1819
//#define evprintf printf
1920
#define evprintf(...)
2021

2122
char invalid_code[0x100000];
22-
u32 event_cycles[7];
23+
u32 event_cycles[PSXINT_COUNT];
2324

2425
static void schedule_timeslice(void)
2526
{

‎libpcsxcore/new_dynarec/pcsxmem.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -134,7 +134,7 @@ static void io_write_imask16(u32 value)
134134
{
135135
psxHu16ref(0x1074) = value;
136136
if (psxHu16ref(0x1070) & value)
137-
new_dyna_set_event(6, 1);
137+
new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
138138
}
139139

140140
static void io_write_ireg32(u32 value)
@@ -148,7 +148,7 @@ static void io_write_imask32(u32 value)
148148
{
149149
psxHu32ref(0x1074) = value;
150150
if (psxHu32ref(0x1070) & value)
151-
new_dyna_set_event(6, 1);
151+
new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
152152
}
153153

154154
static void io_write_dma_icr32(u32 value)

‎libpcsxcore/psxdma.h

+12-12
Original file line numberDiff line numberDiff line change
@@ -30,24 +30,24 @@ extern "C" {
3030
#include "psxmem.h"
3131

3232
#define GPUDMA_INT(eCycle) { \
33-
psxRegs.interrupt |= 0x01000000; \
34-
psxRegs.intCycle[3 + 24 + 1] = eCycle; \
35-
psxRegs.intCycle[3 + 24] = psxRegs.cycle; \
36-
new_dyna_set_event(3, eCycle); \
33+
psxRegs.interrupt |= (1 << PSXINT_GPUDMA); \
34+
psxRegs.intCycle[PSXINT_GPUDMA].cycle = eCycle; \
35+
psxRegs.intCycle[PSXINT_GPUDMA].sCycle = psxRegs.cycle; \
36+
new_dyna_set_event(PSXINT_GPUDMA, eCycle); \
3737
}
3838

3939
#define SPUDMA_INT(eCycle) { \
40-
psxRegs.interrupt |= 0x04000000; \
41-
psxRegs.intCycle[1 + 24 + 1] = eCycle; \
42-
psxRegs.intCycle[1 + 24] = psxRegs.cycle; \
43-
new_dyna_set_event(5, eCycle); \
40+
psxRegs.interrupt |= (1 << PSXINT_SPUDMA); \
41+
psxRegs.intCycle[PSXINT_SPUDMA].cycle = eCycle; \
42+
psxRegs.intCycle[PSXINT_SPUDMA].sCycle = psxRegs.cycle; \
43+
new_dyna_set_event(PSXINT_SPUDMA, eCycle); \
4444
}
4545

4646
#define MDECOUTDMA_INT(eCycle) { \
47-
psxRegs.interrupt |= 0x02000000; \
48-
psxRegs.intCycle[5 + 24 + 1] = eCycle; \
49-
psxRegs.intCycle[5 + 24] = psxRegs.cycle; \
50-
new_dyna_set_event(4, eCycle); \
47+
psxRegs.interrupt |= (1 << PSXINT_MDECOUTDMA); \
48+
psxRegs.intCycle[PSXINT_MDECOUTDMA].cycle = eCycle; \
49+
psxRegs.intCycle[PSXINT_MDECOUTDMA].sCycle = psxRegs.cycle; \
50+
new_dyna_set_event(PSXINT_MDECOUTDMA, eCycle); \
5151
}
5252

5353
void psxDma2(u32 madr, u32 bcr, u32 chcr);

‎libpcsxcore/psxhw.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -432,7 +432,7 @@ void psxHwWrite16(u32 add, u16 value) {
432432
#endif
433433
psxHu16ref(0x1074) = SWAPu16(value);
434434
if (psxHu16ref(0x1070) & value)
435-
new_dyna_set_event(6, 1);
435+
new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
436436
return;
437437

438438
case 0x1f801100:
@@ -546,7 +546,7 @@ void psxHwWrite32(u32 add, u32 value) {
546546
#endif
547547
psxHu32ref(0x1074) = SWAPu32(value);
548548
if (psxHu32ref(0x1070) & value)
549-
new_dyna_set_event(6, 1);
549+
new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
550550
return;
551551

552552
#ifdef PSXHW_LOG

‎libpcsxcore/psxmem.h

-14
Original file line numberDiff line numberDiff line change
@@ -138,20 +138,6 @@ void psxMemWrite16(u32 mem, u16 value);
138138
void psxMemWrite32(u32 mem, u32 value);
139139
void *psxMemPointer(u32 mem);
140140

141-
extern u32 event_cycles[7];
142-
extern u32 next_interupt;
143-
144-
#define new_dyna_set_event(e, c) { \
145-
s32 c_ = c; \
146-
u32 abs_ = psxRegs.cycle + c_; \
147-
s32 odi_ = next_interupt - psxRegs.cycle; \
148-
event_cycles[e] = abs_; \
149-
if (c_ < odi_) { \
150-
/*printf("%u: next_interupt %d -> %d (%u)\n", psxRegs.cycle, odi_, c_, abs_);*/ \
151-
next_interupt = abs_; \
152-
} \
153-
}
154-
155141
#ifdef __cplusplus
156142
}
157143
#endif

‎libpcsxcore/r3000a.c

+18-18
Original file line numberDiff line numberDiff line change
@@ -115,39 +115,39 @@ void psxBranchTest() {
115115
psxRcntUpdate();
116116

117117
if (psxRegs.interrupt) {
118-
if ((psxRegs.interrupt & 0x80) && !Config.Sio) { // sio
119-
if ((psxRegs.cycle - psxRegs.intCycle[7]) >= psxRegs.intCycle[7 + 1]) {
120-
psxRegs.interrupt &= ~0x80;
118+
if ((psxRegs.interrupt & (1 << PSXINT_SIO)) && !Config.Sio) { // sio
119+
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SIO].sCycle) >= psxRegs.intCycle[PSXINT_SIO].cycle) {
120+
psxRegs.interrupt &= ~(1 << PSXINT_SIO);
121121
sioInterrupt();
122122
}
123123
}
124-
if (psxRegs.interrupt & 0x04) { // cdr
125-
if ((psxRegs.cycle - psxRegs.intCycle[2]) >= psxRegs.intCycle[2 + 1]) {
126-
psxRegs.interrupt &= ~0x04;
124+
if (psxRegs.interrupt & (1 << PSXINT_CDR)) { // cdr
125+
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDR].sCycle) >= psxRegs.intCycle[PSXINT_CDR].cycle) {
126+
psxRegs.interrupt &= ~(1 << PSXINT_CDR);
127127
cdrInterrupt();
128128
}
129129
}
130-
if (psxRegs.interrupt & 0x040000) { // cdr read
131-
if ((psxRegs.cycle - psxRegs.intCycle[2 + 16]) >= psxRegs.intCycle[2 + 16 + 1]) {
132-
psxRegs.interrupt &= ~0x040000;
130+
if (psxRegs.interrupt & (1 << PSXINT_CDREAD)) { // cdr read
131+
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDREAD].sCycle) >= psxRegs.intCycle[PSXINT_CDREAD].cycle) {
132+
psxRegs.interrupt &= ~(1 << PSXINT_CDREAD);
133133
cdrReadInterrupt();
134134
}
135135
}
136-
if (psxRegs.interrupt & 0x01000000) { // gpu dma
137-
if ((psxRegs.cycle - psxRegs.intCycle[3 + 24]) >= psxRegs.intCycle[3 + 24 + 1]) {
138-
psxRegs.interrupt &= ~0x01000000;
136+
if (psxRegs.interrupt & (1 << PSXINT_GPUDMA)) { // gpu dma
137+
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUDMA].cycle) {
138+
psxRegs.interrupt &= ~(1 << PSXINT_GPUDMA);
139139
gpuInterrupt();
140140
}
141141
}
142-
if (psxRegs.interrupt & 0x02000000) { // mdec out dma
143-
if ((psxRegs.cycle - psxRegs.intCycle[5 + 24]) >= psxRegs.intCycle[5 + 24 + 1]) {
144-
psxRegs.interrupt &= ~0x02000000;
142+
if (psxRegs.interrupt & (1 << PSXINT_MDECOUTDMA)) { // mdec out dma
143+
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECOUTDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECOUTDMA].cycle) {
144+
psxRegs.interrupt &= ~(1 << PSXINT_MDECOUTDMA);
145145
mdec1Interrupt();
146146
}
147147
}
148-
if (psxRegs.interrupt & 0x04000000) { // spu dma
149-
if ((psxRegs.cycle - psxRegs.intCycle[1 + 24]) >= psxRegs.intCycle[1 + 24 + 1]) {
150-
psxRegs.interrupt &= ~0x04000000;
148+
if (psxRegs.interrupt & (1 << PSXINT_SPUDMA)) { // spu dma
149+
if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_SPUDMA].cycle) {
150+
psxRegs.interrupt &= ~(1 << PSXINT_SPUDMA);
151151
spuInterrupt();
152152
}
153153
}

‎libpcsxcore/r3000a.h

+27-1
Original file line numberDiff line numberDiff line change
@@ -145,6 +145,17 @@ typedef union {
145145
PAIR p[32];
146146
} psxCP2Ctrl;
147147

148+
enum {
149+
PSXINT_SIO = 0,
150+
PSXINT_CDR,
151+
PSXINT_CDREAD,
152+
PSXINT_GPUDMA,
153+
PSXINT_MDECOUTDMA,
154+
PSXINT_SPUDMA,
155+
PSXINT_NEWDRC_CHECK,
156+
PSXINT_COUNT
157+
};
158+
148159
typedef struct {
149160
psxGPRRegs GPR; /* General Purpose Registers */
150161
psxCP0Regs CP0; /* Coprocessor0 Registers */
@@ -154,11 +165,26 @@ typedef struct {
154165
u32 code; /* The instruction */
155166
u32 cycle;
156167
u32 interrupt;
157-
u32 intCycle[32];
168+
struct { u32 sCycle, cycle; } intCycle[32];
158169
} psxRegisters;
159170

160171
extern psxRegisters psxRegs;
161172

173+
/* new_dynarec stuff */
174+
extern u32 event_cycles[PSXINT_COUNT];
175+
extern u32 next_interupt;
176+
177+
#define new_dyna_set_event(e, c) { \
178+
s32 c_ = c; \
179+
u32 abs_ = psxRegs.cycle + c_; \
180+
s32 odi_ = next_interupt - psxRegs.cycle; \
181+
event_cycles[e] = abs_; \
182+
if (c_ < odi_) { \
183+
/*printf("%u: next_interupt %d -> %d (%u)\n", psxRegs.cycle, odi_, c_, abs_);*/ \
184+
next_interupt = abs_; \
185+
} \
186+
}
187+
162188
#if defined(__BIGENDIAN__)
163189

164190
#define _i32(x) *(s32 *)&x

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