Skip to content

Commit 5f1b98b

Browse files
kapi-nokapi-no
committed
samples: benchmark: coremark: add FLPR support for nRF54L15 DK
Added the FLPR core support for the nRF54L15 DK board target in the CoreMark sample. Ref: NCSDK-30327 Signed-off-by: Kamil Piszczek <Kamil.Piszczek@nordicsemi.no>
1 parent cbeb54f commit 5f1b98b

8 files changed

+160
-14
lines changed

‎doc/nrf/releases_and_maturity/releases/release-notes-changelog.rst

+4-1
Original file line numberDiff line numberDiff line change
@@ -528,7 +528,10 @@ Other samples
528528

529529
* :ref:`coremark_sample` sample:
530530

531-
* Added support for the nRF54L05 and nRF54L10 SoCs (emulated on nRF54L15 DK).
531+
* Added:
532+
533+
* Support for the nRF54L05 and nRF54L10 SoCs (emulated on nRF54L15 DK).
534+
* FLPR core support for the :ref:`zephyr:nrf54l15dk_nrf54l15` board target.
532535

533536
Drivers
534537
=======

‎samples/benchmarks/coremark/Kconfig

+12-3
Original file line numberDiff line numberDiff line change
@@ -6,10 +6,19 @@
66

77
menu "CoreMark sample"
88

9+
config APP_BUTTON_AND_LED_SUPPORTED
10+
bool
11+
default y if $(dt_alias_enabled,button) && $(dt_alias_enabled,led)
12+
help
13+
The VPR cores do not have button and LED support on the nRF54H20 DK as GPIO pins
14+
connected to buttons and LEDs share the same GPIO port. The Zephyr framework does
15+
not support individual GPIO pin assignments. For instance, it is not possible to
16+
assign Button 0 to the application core and Button 2 to the FLPR core on
17+
the nRF54H20 DK as these buttons share the same GPIO port.
18+
919
config APP_MODE_FLASH_AND_RUN
10-
bool "Run CoreMark benchmark on start up" if \
11-
!(SOC_NRF54H20_CPUPPR)
12-
default y if SOC_NRF54H20_CPUPPR
20+
bool "Run CoreMark benchmark on start up" if APP_BUTTON_AND_LED_SUPPORTED
21+
default y if !APP_BUTTON_AND_LED_SUPPORTED
1322
help
1423
If enabled, CoreMark will start execution immediately after the CPU starts up.
1524
It also disables LEDs and buttons.

‎samples/benchmarks/coremark/Kconfig.sysbuild

+5
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,11 @@
66

77
source "share/sysbuild/Kconfig"
88

9+
config APP_CPUFLPR_RUN
10+
bool "Run the CoreMark benchmark on the FLPR core"
11+
depends on SUPPORT_FLPRCORE && !SOC_NRF54H20_CPUAPP && !SOC_NRF54L05_CPUAPP && !SOC_NRF54L10_CPUAPP
12+
default y
13+
914
config APP_CPUNET_RUN
1015
bool "Run the CoreMark benchmark on the network or radio core"
1116
depends on SUPPORT_NETCORE

‎samples/benchmarks/coremark/README.rst

+50-10
Original file line numberDiff line numberDiff line change
@@ -77,33 +77,55 @@ Each target CPU has an assigned button responsible for starting the benchmark an
7777

7878
.. tabs::
7979

80-
.. group-tab:: nRF52 and nRF53 DKs
80+
.. group-tab:: nRF52 DKs
81+
82+
Button 1:
83+
Start the benchmark run on the application core.
84+
85+
LED 1:
86+
Indicates ``test in progress`` on the application core.
87+
88+
.. group-tab:: nRF53 DKs
8189

8290
Button 1:
8391
Start the benchmark run on the application core.
8492

8593
Button 2:
86-
Start the benchmark run on the network or radio core.
94+
Start the benchmark run on the network core.
8795

8896
LED 1:
8997
Indicates ``test in progress`` on the application core.
9098

9199
LED 2:
92-
Indicates ``test in progress`` on the network or radio core.
100+
Indicates ``test in progress`` on the network core.
93101

94-
.. group-tab:: nRF54 DKs
102+
.. group-tab:: nRF54L DKs
103+
104+
Button 0:
105+
Start the benchmark run on the application core.
106+
107+
Button 3 (only supported for the ``nrf54l15dk/nrf54l15/cpuapp`` board target):
108+
Start the benchmark run on the FLPR core.
109+
110+
LED 0:
111+
Indicates ``test in progress`` on the application core.
112+
113+
LED 3 (only supported for the ``nrf54l15dk/nrf54l15/cpuapp`` board target):
114+
Indicates ``test in progress`` on the FLPR core.
115+
116+
.. group-tab:: nRF54H DKs
95117

96118
Button 0:
97119
Start the benchmark run on the application core.
98120

99121
Button 1:
100-
Start the benchmark run on the network or radio core.
122+
Start the benchmark run on the radio core.
101123

102124
LED 0:
103125
Indicates ``test in progress`` on the application core.
104126

105127
LED 1:
106-
Indicates ``test in progress`` on the network or radio core.
128+
Indicates ``test in progress`` on the radio core.
107129

108130
.. _coremark_configuration:
109131

@@ -171,18 +193,36 @@ CONFIG_APP_MODE_FLASH_AND_RUN - Start CoreMark sample automatically after flashi
171193
Otherwise, it will wait for the button press.
172194

173195
.. note::
174-
The :kconfig:option:`CONFIG_APP_MODE_FLASH_AND_RUN` Kconfig option is always enabled for the PPR core.
175-
This core does not use buttons.
196+
The :kconfig:option:`CONFIG_APP_MODE_FLASH_AND_RUN` Kconfig option is always enabled for the PPR core on the ``nrf54h20dk/nrf54h20/cpuapp`` board target.
197+
This core on the ``nrf54h20dk/nrf54h20/cpuapp`` board target does not use buttons and LEDs.
198+
199+
.. _SB_CONFIG_APP_CPUFLPR_RUN:
200+
201+
SB_CONFIG_APP_CPUFLPR_RUN - Enable execution for the FLPR core
202+
Enable the benchmark execution also for the FLPR core.
203+
This option is only available for board targets that support the FLPR core (for example, ``nrf54l15dk/nrf54l15/cpuapp``) in this sample.
204+
205+
.. note::
206+
FLPR code is run from RAM.
207+
208+
This option is not supported for the following board targets that include an SoC with the FLPR core:
209+
210+
* ``nrf54h20dk/nrf54h20/cpuapp``
211+
* ``nrf54l15dk/nrf54l05/cpuapp``
212+
* ``nrf54l15dk/nrf54l10/cpuapp``
176213

177214
.. _SB_CONFIG_APP_CPUNET_RUN:
178215

179216
SB_CONFIG_APP_CPUNET_RUN - Enable execution for the network core or the radio core
180-
Enable the benchmark execution for the network core for targets with the nRF53 Series SoCs, and for the radio core on targets with the nRF54H20 SoCs.
217+
Enable the benchmark execution also for the network core or the radio core.
218+
This option is only available for board targets that support the network core (for example, ``nrf5340dk/nrf5340/cpuapp``) or radio core (for example, ``nrf54h20dk/nrf54h20/cpuapp``) in this sample .
181219

182220
.. _SB_CONFIG_APP_CPUPPR_RUN:
183221

184222
SB_CONFIG_APP_CPUPPR_RUN - Enable execution for the PPR core
185-
Enable the benchmark execution also for the PPR core for targets with the nRF54H20 SoCs.
223+
Enable the benchmark execution also for the PPR core.
224+
This option is only available for board targets that support the PPR core (for example, ``nrf54h20dk/nrf54h20/cpuapp``) in this sample.
225+
186226

187227
.. note::
188228
PPR code is run from RAM.

‎samples/benchmarks/coremark/boards/nrf54l15dk_nrf54l15_cpuapp.overlay

+52
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,52 @@
1+
/*
2+
* Copyright (c) 2025 Nordic Semiconductor ASA
3+
*
4+
* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
5+
*/
6+
7+
#include "app_aliases_common.overlay"
8+
9+
/* The following configuration is required to run the CPUFLPR core.
10+
* It is imported from the nordic-flpr snippet.
11+
*/
12+
/ {
13+
soc {
14+
reserved-memory {
15+
#address-cells = <1>;
16+
#size-cells = <1>;
17+
cpuflpr_code_partition: image@165000 {
18+
/* FLPR core code partition */
19+
reg = <0x165000 DT_SIZE_K(96)>;
20+
};
21+
};
22+
23+
cpuflpr_sram_code_data: memory@20028000 {
24+
compatible = "mmio-sram";
25+
reg = <0x20028000 DT_SIZE_K(96)>;
26+
#address-cells = <1>;
27+
#size-cells = <1>;
28+
ranges = <0x0 0x20028000 0x18000>;
29+
};
30+
};
31+
};
32+
33+
&cpuapp_sram {
34+
reg = <0x20000000 DT_SIZE_K(160)>;
35+
ranges = <0x0 0x20000000 0x28000>;
36+
};
37+
38+
&cpuflpr_vpr {
39+
status = "okay";
40+
execution-memory = <&cpuflpr_sram_code_data>;
41+
source-memory = <&cpuflpr_code_partition>;
42+
};
43+
44+
&cpuapp_vevif_tx {
45+
status = "okay";
46+
};
47+
48+
/* The same set of GPIO and GPIOTE DTS nodes are enabled in the cpuapp and the cpuflpr targets.
49+
* This is done to allow control over one Button and one LED in each core. The benchmark code is
50+
* responsible for ensuring that each core exclusively uses the individual GPIO pin and the GPIOTE
51+
* instance that may be used with the GPIO pin (Button).
52+
*/

‎samples/benchmarks/coremark/boards/nrf54l15dk_nrf54l15_cpuflpr.conf

+8
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
#
2+
# Copyright (c) 2025 Nordic Semiconductor ASA
3+
#
4+
# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
5+
6+
CONFIG_COREMARK_ITERATIONS=4000
7+
8+
CONFIG_LOG_MODE_IMMEDIATE=y

‎samples/benchmarks/coremark/boards/nrf54l15dk_nrf54l15_cpuflpr.overlay

+18
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
/*
2+
* Copyright (c) 2025 Nordic Semiconductor ASA
3+
*
4+
* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
5+
*/
6+
7+
/ {
8+
aliases {
9+
button = &button3;
10+
led = &led3;
11+
};
12+
};
13+
14+
/* The same set of GPIO and GPIOTE DTS nodes are enabled in the cpuapp and the cpuflpr targets.
15+
* This is done to allow control over one Button and one LED in each core. The benchmark code is
16+
* responsible for ensuring that each core exclusively uses the individual GPIO pin and the GPIOTE
17+
* instance that may be used with the GPIO pin (Button).
18+
*/

‎samples/benchmarks/coremark/sysbuild.cmake

+11
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,17 @@
55

66
include_guard(GLOBAL)
77

8+
if(SB_CONFIG_APP_CPUFLPR_RUN)
9+
10+
ExternalZephyrProject_Add(
11+
APPLICATION coremark_${SB_CONFIG_FLPRCORE_REMOTE_BOARD_TARGET_CPUCLUSTER}
12+
SOURCE_DIR ${APP_DIR}
13+
BOARD ${SB_CONFIG_BOARD}/${SB_CONFIG_SOC}/${SB_CONFIG_FLPRCORE_REMOTE_BOARD_TARGET_CPUCLUSTER}
14+
BOARD_REVISION ${BOARD_REVISION}
15+
)
16+
17+
endif()
18+
819
if(SB_CONFIG_APP_CPUNET_RUN)
920

1021
ExternalZephyrProject_Add(

0 commit comments

Comments
 (0)