tests: drivers: uart: uart_baudrate_test: keep high freq

Prevent enabled clock control to scale down freq,
as this affects gpio polling time.

Signed-off-by: Piotr Kosycarz <piotr.kosycarz@nordicsemi.no>

Author: nordic-piks

tests/drivers/uart/uart_baudrate_test/src/main.c

@@ -200,6 +200,7 @@ static void check_timing(const struct gpio_dt_spec *gpio_dt, uint32_t baudrate)
 	} else {
 		TC_PRINT("Not checking diviation due to lost start of start bit\n");
 	}
+	zassert_true(false, "");
 }
 
 ZTEST(uart_baudrate_test, test_08_2400)

tests/drivers/uart/uart_baudrate_test/testcase.yaml

@@ -16,6 +16,8 @@ tests:
     extra_configs:
       - CONFIG_PM_DEVICE=y
       - CONFIG_PM_DEVICE_RUNTIME=y
+      - CONFIG_CLOCK_CONTROL_NRF2_GLOBAL_HSFLL_REQ_LOW_FREQ=n
+      - CONFIG_NRFS_LOCAL_DOMAIN_DVFS_SCALE_DOWN_AFTER_INIT=n
   drivers.uart.baudrate_test.uart135:
     platform_allow:
       - nrf54h20dk/nrf54h20/cpuapp