-
Notifications
You must be signed in to change notification settings - Fork 1
/
Copy pathuhdl.v
300 lines (283 loc) · 9.61 KB
/
uhdl.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
// uhdl.v --- ---!!!
`timescale 1ns/1ps
`default_nettype none
`define enable_mmc
`define enable_vga
`define enable_ps2
`define enable_spy_port
/* verilator lint_off SELRANGE */
/* verilator lint_off IMPLICIT */
/* verilator lint_off PINMISSING */
/* verilator lint_off WIDTH */
module uhdl;
reg boot;
reg reset;
wire [11:0] bd_state;
wire [11:0] ms_x, ms_y;
wire [15:0] bd_data_bd2cpu;
wire [15:0] bd_data_cpu2bd;
wire [15:0] kb_data;
wire [15:0] spy_bd_data_bd2cpu;
wire [15:0] spy_bd_data_cpu2bd;
wire [15:0] spy_bd_state;
wire [15:0] spy_in;
wire [15:0] spy_out;
wire [15:0] sram1_in;
wire [15:0] sram2_in;
wire [1:0] bd_cmd;
wire [1:0] spy_bd_cmd;
wire [21:0] busint_addr;
wire [23:0] bd_addr;
wire [23:0] spy_bd_addr;
wire [2:0] ms_button;
wire [31:0] busint_bus;
wire [31:0] md;
wire [31:0] sdram_data_in;
wire [31:0] sdram_data_rc2cpu;
wire [31:0] vram_cpu_data_in;
wire [3:0] dots;
wire [3:0] rc_state;
wire [48:0] mcr_data_in;
wire [4:0] eadr;
wire bd_bsy;
wire bd_err;
wire bd_iordy;
wire bd_rd;
wire bd_rdy;
wire bd_start;
wire bd_wr;
wire bus_int;
wire clk50;
wire cpu_clk;
wire dbread, dbwrite;
wire dcm_reset;
wire halt;
wire interrupt;
wire kb_ps2_clk_in;
wire kb_ps2_data_in;
wire kb_ready;
wire loadmd;
wire lpddr_reset;
wire memack;
wire memrq;
wire ms_ps2_clk_in;
wire ms_ps2_clk_out;
wire ms_ps2_data_in;
wire ms_ps2_data_out;
wire ms_ps2_dir;
wire ms_ready;
wire vga_clk;
wire vga_clk_locked;
wire spy_bd_bsy;
wire spy_bd_err;
wire spy_bd_iordy;
wire spy_bd_rd;
wire spy_bd_rdy;
wire spy_bd_start;
wire spy_bd_wr;
wire sysclk_buf;
wire vga_reset;
wire wrcyc;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] bus_state; // From uhdl_common of uhdl_common.v
wire [15:0] busint_spyout; // From uhdl_common of uhdl_common.v
wire [4:0] disk_state; // From uhdl_common of uhdl_common.v
wire fetch; // From uhdl_common of uhdl_common.v
wire [13:0] mcr_addr; // From uhdl_common of uhdl_common.v
wire [48:0] mcr_data_out; // From ram_controller of ram_controller.v, ...
wire mcr_done; // From ram_controller of ram_controller.v
wire mcr_ready; // From ram_controller of ram_controller.v
wire mcr_write; // From uhdl_common of uhdl_common.v
wire mmc_cs; // From uhdl_common of uhdl_common.v
wire mmc_do; // From uhdl_common of uhdl_common.v
wire mmc_sclk; // From uhdl_common of uhdl_common.v
wire ms_ps2_clk; // To/From uhdl_common of uhdl_common.v
wire ms_ps2_data; // To/From uhdl_common of uhdl_common.v
wire prefetch; // From uhdl_common of uhdl_common.v
wire rs232_txd; // From uhdl_common of uhdl_common.v
wire [21:0] sdram_addr; // From uhdl_common of uhdl_common.v
wire [31:0] sdram_data_cpu2rc; // From uhdl_common of uhdl_common.v
wire [31:0] sdram_data_out; // From ram_controller of ram_controller.v
wire sdram_done; // From ram_controller of ram_controller.v
wire sdram_ready; // From ram_controller of ram_controller.v
wire sdram_req; // From uhdl_common of uhdl_common.v
wire sdram_write; // From uhdl_common of uhdl_common.v
wire spy_rd; // From uhdl_common of uhdl_common.v
wire [3:0] spy_reg; // From uhdl_common of uhdl_common.v
wire spy_wr; // From uhdl_common of uhdl_common.v
wire sram1_ce_n; // From ram_controller of ram_controller.v
wire sram1_lb_n; // From ram_controller of ram_controller.v
wire [15:0] sram1_out; // From ram_controller of ram_controller.v
wire sram1_ub_n; // From ram_controller of ram_controller.v
wire sram2_ce_n; // From ram_controller of ram_controller.v
wire sram2_lb_n; // From ram_controller of ram_controller.v
wire [15:0] sram2_out; // From ram_controller of ram_controller.v
wire sram2_ub_n; // From ram_controller of ram_controller.v
wire [17:0] sram_a; // From ram_controller of ram_controller.v
wire sram_oe_n; // From ram_controller of ram_controller.v
wire sram_we_n; // From ram_controller of ram_controller.v
wire vga_b; // From uhdl_common of uhdl_common.v
wire vga_blank; // From uhdl_common of uhdl_common.v
wire vga_g; // From uhdl_common of uhdl_common.v
wire vga_hsync; // From uhdl_common of uhdl_common.v
wire vga_r; // From uhdl_common of uhdl_common.v
wire vga_vsync; // From uhdl_common of uhdl_common.v
wire [14:0] vram_cpu_addr; // From uhdl_common of uhdl_common.v
wire [31:0] vram_cpu_data_out; // From ram_controller of ram_controller.v, ...
wire vram_cpu_done; // From ram_controller of ram_controller.v
wire vram_cpu_ready; // From ram_controller of ram_controller.v
wire vram_cpu_req; // From uhdl_common of uhdl_common.v
wire vram_cpu_write; // From uhdl_common of uhdl_common.v
wire [14:0] vram_vga_addr; // From uhdl_common of uhdl_common.v
wire [31:0] vram_vga_data_out; // From ram_controller of ram_controller.v
wire vram_vga_ready; // From ram_controller of ram_controller.v
wire vram_vga_req; // From uhdl_common of uhdl_common.v
// End of automatics
////////////////////////////////////////////////////////////////////////////////
integer cycles;
always @(posedge uhdl_common.cpu.clk) begin
if (uhdl_common.cpu.state == 6'b100000 && ~uhdl_common.cpu.iwrited && ~uhdl_common.cpu.cadr_contrl.inop) begin
cycles = cycles + 1;
end
end
assign halt = 0;
assign eadr = 5'b0;
assign dbread = 0;
assign dbwrite = 0;
assign spyin = 0;
assign kb_ready = 0;
assign kb_data = 16'b0;
assign ms_ready = 0;
assign ms_x = 12'b0;
assign ms_y = 12'b0;
assign ms_button = 3'b0;
ram_controller ram_controller(/*AUTOINST*/
// Outputs
.sram1_out (sram1_out[15:0]),
.sram2_out (sram2_out[15:0]),
.sram_a (sram_a[17:0]),
.sdram_data_out (sdram_data_out[31:0]),
.vram_cpu_data_out (vram_cpu_data_out[31:0]),
.vram_vga_data_out (vram_vga_data_out[31:0]),
.mcr_data_out (mcr_data_out[48:0]),
.mcr_done (mcr_done),
.mcr_ready (mcr_ready),
.sdram_done (sdram_done),
.sdram_ready (sdram_ready),
.sram1_ce_n (sram1_ce_n),
.sram1_ub_n (sram1_ub_n),
.sram1_lb_n (sram1_lb_n),
.sram2_ce_n (sram2_ce_n),
.sram2_ub_n (sram2_ub_n),
.sram2_lb_n (sram2_lb_n),
.sram_oe_n (sram_oe_n),
.sram_we_n (sram_we_n),
.vram_cpu_done (vram_cpu_done),
.vram_cpu_ready (vram_cpu_ready),
.vram_vga_ready (vram_vga_ready),
// Inputs
.mcr_addr (mcr_addr[13:0]),
.vram_cpu_addr (vram_cpu_addr[14:0]),
.vram_vga_addr (vram_vga_addr[14:0]),
.sram1_in (sram1_in[15:0]),
.sram2_in (sram2_in[15:0]),
.sdram_addr (sdram_addr[21:0]),
.sdram_data_in (sdram_data_in[31:0]),
.vram_cpu_data_in (vram_cpu_data_in[31:0]),
.mcr_data_in (mcr_data_in[48:0]),
.clk (clk),
.cpu_clk (cpu_clk),
.fetch (fetch),
.mcr_write (mcr_write),
.prefetch (prefetch),
.reset (reset),
.sdram_req (sdram_req),
.sdram_write (sdram_write),
.vga_clk (vga_clk),
.vram_cpu_req (vram_cpu_req),
.vram_cpu_write (vram_cpu_write),
.vram_vga_req (vram_vga_req));
uhdl_common uhdl_common(/*AUTOINST*/
// Outputs
.sdram_addr (sdram_addr[21:0]),
.sdram_data_cpu2rc (sdram_data_cpu2rc[31:0]),
.sdram_req (sdram_req),
.sdram_write (sdram_write),
.vram_cpu_addr (vram_cpu_addr[14:0]),
.vram_cpu_data_out (vram_cpu_data_out[31:0]),
.vram_cpu_req (vram_cpu_req),
.vram_cpu_write (vram_cpu_write),
.spy_reg (spy_reg[3:0]),
.busint_spyout (busint_spyout[15:0]),
.spy_rd (spy_rd),
.spy_wr (spy_wr),
.disk_state (disk_state[4:0]),
.bus_state (bus_state[3:0]),
.fetch (fetch),
.prefetch (prefetch),
.mcr_addr (mcr_addr[13:0]),
.mcr_data_out (mcr_data_out[48:0]),
.mcr_write (mcr_write),
.mmc_cs (mmc_cs),
.mmc_do (mmc_do),
.mmc_sclk (mmc_sclk),
.vram_vga_addr (vram_vga_addr[14:0]),
.vram_vga_req (vram_vga_req),
.vga_blank (vga_blank),
.vga_r (vga_r),
.vga_g (vga_g),
.vga_b (vga_b),
.vga_hsync (vga_hsync),
.vga_vsync (vga_vsync),
.rs232_txd (rs232_txd),
// Inouts
.ms_ps2_clk (ms_ps2_clk),
.ms_ps2_data (ms_ps2_data),
// Inputs
.clk50 (clk50),
.reset (reset),
.sdram_data_rc2cpu (sdram_data_rc2cpu[31:0]),
.sdram_done (sdram_done),
.sdram_ready (sdram_ready),
.vram_cpu_data_in (vram_cpu_data_in[31:0]),
.vram_cpu_done (vram_cpu_done),
.vram_cpu_ready (vram_cpu_ready),
.cpu_clk (cpu_clk),
.boot (boot),
.halt (halt),
.interrupt (interrupt),
.mcr_data_in (mcr_data_in[48:0]),
.mcr_ready (mcr_ready),
.mcr_done (mcr_done),
.mmc_di (mmc_di),
.vram_vga_data_out (vram_vga_data_out[31:0]),
.vram_vga_ready (vram_vga_ready),
.vga_clk (vga_clk),
.kb_ps2_clk (kb_ps2_clk),
.kb_ps2_data (kb_ps2_data),
.rs232_rxd (rs232_rxd));
vga_dpi vga_dpi
(
.vsync(vga_hsync),
.hsync(vga_vsync),
.r(vga_red),
.g(vga_grn),
.b(vga_blu),
/*AUTOINST*/
// Inputs
.clk (clk));
mmc_dpi mmc_dpi
(
.clk(cpu_clk),
.mmc_di(mmc_do),
.mmc_do(mmc_di),
/*AUTOINST*/
// Inputs
.mmc_sclk (mmc_sclk),
.mmc_cs (mmc_cs));
endmodule
`default_nettype wire
// Local Variables:
// verilog-library-directories: (".")
// End: