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22 | 22 | #if CONFIG_OPENTHREAD_ENABLED
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23 | 23 | #include "esp_openthread_types.h"
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24 | 24 |
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| 25 | +#if CONFIG_OPENTHREAD_RADIO_NATIVE |
25 | 26 | #define ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG() \
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26 | 27 | { \
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27 | 28 | .radio_mode = RADIO_MODE_NATIVE, \
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28 | 29 | }
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| 30 | +#elif CONFIG_OPENTHREAD_RADIO_SPINEL_UART |
| 31 | +#define ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG() \ |
| 32 | + { \ |
| 33 | + .radio_mode = RADIO_MODE_UART_RCP, \ |
| 34 | + .radio_uart_config = { \ |
| 35 | + .port = UART_NUM_1, \ |
| 36 | + .uart_config = \ |
| 37 | + { \ |
| 38 | + .baud_rate = 460800, \ |
| 39 | + .data_bits = UART_DATA_8_BITS, \ |
| 40 | + .parity = UART_PARITY_DISABLE, \ |
| 41 | + .stop_bits = UART_STOP_BITS_1, \ |
| 42 | + .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, \ |
| 43 | + .rx_flow_ctrl_thresh = 0, \ |
| 44 | + .source_clk = UART_SCLK_DEFAULT, \ |
| 45 | + }, \ |
| 46 | + .rx_pin = GPIO_NUM_17, \ |
| 47 | + .tx_pin = GPIO_NUM_18, \ |
| 48 | + }, \ |
| 49 | + } |
| 50 | +#else |
| 51 | +#define ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG() \ |
| 52 | + { \ |
| 53 | + .radio_mode = RADIO_MODE_SPI_RCP, \ |
| 54 | + .radio_spi_config = { \ |
| 55 | + .host_device = SPI2_HOST, \ |
| 56 | + .dma_channel = 2, \ |
| 57 | + .spi_interface = \ |
| 58 | + { \ |
| 59 | + .mosi_io_num = 11, \ |
| 60 | + .sclk_io_num = 12, \ |
| 61 | + .miso_io_num = 13, \ |
| 62 | + }, \ |
| 63 | + .spi_device = \ |
| 64 | + { \ |
| 65 | + .cs_ena_pretrans = 2, \ |
| 66 | + .input_delay_ns = 100, \ |
| 67 | + .mode = 0, \ |
| 68 | + .clock_speed_hz = 2500 * 1000, \ |
| 69 | + .spics_io_num = 10, \ |
| 70 | + .queue_size = 5, \ |
| 71 | + }, \ |
| 72 | + .intr_pin = 8, \ |
| 73 | + }, \ |
| 74 | + } |
| 75 | +#endif // CONFIG_OPENTHREAD_RADIO_SPINEL_UART OR CONFIG_OPENTHREAD_RADIO_SPINEL_SPI |
29 | 76 |
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30 | 77 | #define ESP_OPENTHREAD_DEFAULT_HOST_CONFIG() \
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31 | 78 | { \
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36 | 83 | { \
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37 | 84 | .storage_partition_name = "nvs", .netif_queue_size = 10, .task_queue_size = 10, \
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38 | 85 | }
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| 86 | + |
| 87 | +#ifdef CONFIG_OPENTHREAD_BORDER_ROUTER |
| 88 | +#include <esp_rcp_update.h> |
| 89 | +#define RCP_FIRMWARE_DIR "/spiffs/ot_rcp" |
| 90 | + |
| 91 | +#define ESP_OPENTHREAD_RCP_UPDATE_CONFIG() \ |
| 92 | + { \ |
| 93 | + .rcp_type = RCP_TYPE_ESP32H2_UART, .uart_rx_pin = 17, .uart_tx_pin = 18, .uart_port = 1, .uart_baudrate = 115200, \ |
| 94 | + .reset_pin = 7, .boot_pin = 8, .update_baudrate = 460800, .firmware_dir = "/rcp_fw/ot_rcp", .target_chip = ESP32H2_CHIP, \ |
| 95 | + } |
| 96 | +#endif // CONFIG_OPENTHREAD_BORDER_ROUTER |
| 97 | + |
39 | 98 | #endif // CONFIG_OPENTHREAD_ENABLED
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40 | 99 |
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41 | 100 | void ESPOpenThreadInit();
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