Bump gecko-sdk, wifi-sdk and matter support submodules. Small changes to silabs platform code inline with sdk updates. Use latest Docker image version for CI (#32171)

Author: jmartinez-silabs

.github/workflows/examples-efr32.yaml

@@ -38,7 +38,7 @@ jobs:
     if: github.actor != 'restyled-io[bot]'
 
     container:
-      image: ghcr.io/project-chip/chip-build-efr32:35
+      image: ghcr.io/project-chip/chip-build-efr32:36
       volumes:
         - "/tmp/bloat_reports:/tmp/bloat_reports"
     steps:

.github/workflows/release_artifacts.yaml

@@ -68,7 +68,7 @@ jobs:
         runs-on: ubuntu-latest
 
         container:
-            image: ghcr.io/project-chip/chip-build-efr32:35
+            image: ghcr.io/project-chip/chip-build-efr32:36
         steps:
             - name: Checkout
               uses: actions/checkout@v4

.gitmodules

@@ -239,7 +239,7 @@
 [submodule "third_party/silabs/gecko_sdk"]
 	path = third_party/silabs/gecko_sdk
 	url = https://github.com/SiliconLabs/gecko_sdk.git
-	branch = v4.4.0
+	branch = v4.4.1
 	platforms = silabs
 [submodule "third_party/silabs/wiseconnect-wifi-bt-sdk"]
 	path = third_party/silabs/wiseconnect-wifi-bt-sdk
@@ -249,7 +249,7 @@
 [submodule "third_party/silabs/wifi_sdk"]
 	path = third_party/silabs/wifi_sdk
 	url = https://github.com/SiliconLabs/wiseconnect.git
-	branch = v3.1.1
+	branch = v3.1.3
 	platforms = silabs
 [submodule "editline"]
 	path = third_party/editline/repo

examples/platform/silabs/efr32/rs911x/hal/efx32_ncp_host.c

@@ -15,7 +15,6 @@
  *
  ******************************************************************************/
 
-#include "FreeRTOS.h"
 #include "cmsis_os2.h"
 #include "dmadrv.h"
 #include "em_cmu.h"
@@ -37,13 +36,16 @@
 #include "sl_power_manager.h"
 #endif
 
+#define USART_INITSYNC_BAUDRATE 12500000
+
 static bool dma_callback(unsigned int channel, unsigned int sequenceNo, void * userParam);
 
 unsigned int rx_ldma_channel;
 unsigned int tx_ldma_channel;
-osMutexId_t spi_transfer_mutex = 0;
+osMutexId_t ncp_transfer_mutex = 0;
 
 static uint32_t dummy_buffer;
+static sl_si91x_host_init_configuration init_config = { 0 };
 
 // LDMA descriptor and transfer configuration structures for USART TX channel
 LDMA_Descriptor_t ldmaTXDescriptor;
@@ -70,33 +72,22 @@ static bool dma_callback(unsigned int channel, unsigned int sequenceNo, void * u
 static void gpio_interrupt(uint8_t interrupt_number)
 {
     UNUSED_PARAMETER(interrupt_number);
-    sl_si91x_host_set_bus_event(NCP_HOST_BUS_RX_EVENT);
-    //  GPIO_IntClear(0xAAAA);
-}
-
-void sl_si91x_host_set_sleep_indicator(void)
-{
-    GPIO_PinOutSet(SLEEP_CONFIRM_PIN.port, SLEEP_CONFIRM_PIN.pin);
-}
 
-void sl_si91x_host_clear_sleep_indicator(void)
-{
-    GPIO_PinOutClear(SLEEP_CONFIRM_PIN.port, SLEEP_CONFIRM_PIN.pin);
+    if (NULL != init_config.rx_irq)
+    {
+        init_config.rx_irq();
+    }
 }
 
-uint32_t sl_si91x_host_get_wake_indicator(void)
+static void efx32_spi_init(void)
 {
-    return GPIO_PinInGet(WAKE_INDICATOR_PIN.port, WAKE_INDICATOR_PIN.pin);
-}
+    // Default asynchronous initializer (master mode, 1 Mbps, 8-bit data)
+    USART_InitSync_TypeDef init = USART_INITSYNC_DEFAULT;
 
-sl_status_t sl_si91x_host_init(void)
-{
-    // Enable clock (not needed on xG21)
-    CMU_ClockEnable(cmuClock_GPIO, true);
+    init.msbf         = true; // MSB first transmission for SPI compatibility
+    init.autoCsEnable = true; // Allow the USART to assert CS
+    init.baudrate     = USART_INITSYNC_BAUDRATE;
 
-#if SL_SPICTRL_MUX
-    spi_board_init();
-#endif
     // Configure SPI bus pins
     GPIO_PinModeSet(SPI_MISO_PIN.port, SPI_MISO_PIN.pin, gpioModeInput, 0);
     GPIO_PinModeSet(SPI_MOSI_PIN.port, SPI_MOSI_PIN.pin, gpioModePushPull, 0);
@@ -105,12 +96,6 @@ sl_status_t sl_si91x_host_init(void)
     // Enable clock (not needed on xG21)
     CMU_ClockEnable(SPI_USART_CMU_CLOCK, true);
 
-    // Default asynchronous initializer (master mode, 1 Mbps, 8-bit data)
-    USART_InitSync_TypeDef init = USART_INITSYNC_DEFAULT;
-
-    init.msbf         = true; // MSB first transmission for SPI compatibility
-    init.autoCsEnable = true; // Allow the USART to assert CS
-    init.baudrate     = 12500000;
     /*
      * Route USART RX, TX, and CLK to the specified pins.  Note that CS is
      * not controlled by USART so there is no write to the corresponding
@@ -139,33 +124,64 @@ sl_status_t sl_si91x_host_init(void)
     SPI_USART->TIMING |= /*USART_TIMING_TXDELAY_ONE | USART_TIMING_CSSETUP_ONE |*/ USART_TIMING_CSHOLD_ONE;
 
     // SPI_USART->CTRL_SET |= USART_CTRL_SMSDELAY;
+
+    // configure packet pending interrupt priority
+    NVIC_SetPriority(GPIO_ODD_IRQn, PACKET_PENDING_INT_PRI);
+    GPIOINT_CallbackRegister(INTERRUPT_PIN.pin, gpio_interrupt);
+    GPIO_PinModeSet(INTERRUPT_PIN.port, INTERRUPT_PIN.pin, gpioModeInputPullFilter, 0);
+    GPIO_ExtIntConfig(INTERRUPT_PIN.port, INTERRUPT_PIN.pin, INTERRUPT_PIN.pin, true, false, true);
+}
+
+void sl_si91x_host_set_sleep_indicator(void)
+{
+    GPIO_PinOutSet(SLEEP_CONFIRM_PIN.port, SLEEP_CONFIRM_PIN.pin);
+}
+
+void sl_si91x_host_clear_sleep_indicator(void)
+{
+    GPIO_PinOutClear(SLEEP_CONFIRM_PIN.port, SLEEP_CONFIRM_PIN.pin);
+}
+
+uint32_t sl_si91x_host_get_wake_indicator(void)
+{
+    return GPIO_PinInGet(WAKE_INDICATOR_PIN.port, WAKE_INDICATOR_PIN.pin);
+}
+
+sl_status_t sl_si91x_host_init(sl_si91x_host_init_configuration * config)
+{
+    init_config.rx_irq  = config->rx_irq;
+    init_config.rx_done = config->rx_done;
+
+    // Enable clock (not needed on xG21)
+    CMU_ClockEnable(cmuClock_GPIO, true);
+
+#if SL_SPICTRL_MUX
+    spi_board_init();
+#endif
+
     if (transfer_done_semaphore == NULL)
     {
         transfer_done_semaphore = osSemaphoreNew(1, 0, NULL);
     }
 
-    if (spi_transfer_mutex == 0)
+    if (ncp_transfer_mutex == 0)
     {
-        spi_transfer_mutex = osMutexNew(NULL);
+        ncp_transfer_mutex = osMutexNew(NULL);
     }
 
-    DMADRV_Init();
-    DMADRV_AllocateChannel(&rx_ldma_channel, NULL);
-    DMADRV_AllocateChannel(&tx_ldma_channel, NULL);
+    efx32_spi_init();
 
     // Start reset line low
     GPIO_PinModeSet(RESET_PIN.port, RESET_PIN.pin, gpioModePushPull, 0);
 
-    // configure packet pending interrupt priority
-    NVIC_SetPriority(GPIO_ODD_IRQn, PACKET_PENDING_INT_PRI);
-
     // Configure interrupt, sleep and wake confirmation pins
-    GPIOINT_CallbackRegister(INTERRUPT_PIN.pin, gpio_interrupt);
-    GPIO_PinModeSet(INTERRUPT_PIN.port, INTERRUPT_PIN.pin, gpioModeInputPullFilter, 0);
-    GPIO_ExtIntConfig(INTERRUPT_PIN.port, INTERRUPT_PIN.pin, INTERRUPT_PIN.pin, true, false, true);
     GPIO_PinModeSet(SLEEP_CONFIRM_PIN.port, SLEEP_CONFIRM_PIN.pin, gpioModeWiredOrPullDown, 1);
     GPIO_PinModeSet(WAKE_INDICATOR_PIN.port, WAKE_INDICATOR_PIN.pin, gpioModeWiredOrPullDown, 0);
 
+    DMADRV_Init();
+    DMADRV_AllocateChannel(&rx_ldma_channel, NULL);
+    DMADRV_AllocateChannel(&tx_ldma_channel, NULL);
+
     return SL_STATUS_OK;
 }
 
@@ -174,11 +190,7 @@ sl_status_t sl_si91x_host_deinit(void)
     return SL_STATUS_OK;
 }
 
-void sl_si91x_host_enable_high_speed_bus()
-{
-    //  SPI_USART->CTRL_SET |= USART_CTRL_SMSDELAY | USART_CTRL_SSSEARLY;
-    //  USART_BaudrateSyncSet(SPI_USART, 0, 20000000);
-}
+void sl_si91x_host_enable_high_speed_bus() {}
 
 /*==================================================================*/
 /**
@@ -194,7 +206,7 @@ void sl_si91x_host_enable_high_speed_bus()
  */
 sl_status_t sl_si91x_host_spi_transfer(const void * tx_buffer, void * rx_buffer, uint16_t buffer_length)
 {
-    osMutexAcquire(spi_transfer_mutex, 0xFFFFFFFFUL);
+    osMutexAcquire(ncp_transfer_mutex, 0xFFFFFFFFUL);
 
 #if SL_SPICTRL_MUX
     sl_wfx_host_spi_cs_assert();
@@ -268,7 +280,7 @@ sl_status_t sl_si91x_host_spi_transfer(const void * tx_buffer, void * rx_buffer,
         }
     }
 
-    osMutexRelease(spi_transfer_mutex);
+    osMutexRelease(ncp_transfer_mutex);
 #if SL_SPICTRL_MUX
     sl_wfx_host_spi_cs_deassert();
 #endif // SL_SPICTRL_MUX
@@ -288,6 +300,7 @@ void sl_si91x_host_release_from_reset(void)
 
 void sl_si91x_host_enable_bus_interrupt(void)
 {
+    NVIC_ClearPendingIRQ(GPIO_ODD_IRQn);
     NVIC_EnableIRQ(GPIO_ODD_IRQn);
 }
 

examples/platform/silabs/efr32/rs911x/rs9117.gni

@@ -27,7 +27,8 @@ rs9117_src_sapi = [
   "${wifi_sdk_root}/components/device/silabs/si91x/wireless/sl_net/src/sl_net_rsi_utility.c",
   "${wifi_sdk_root}/components/device/silabs/si91x/wireless/sl_net/src/sl_net_si91x_integration_handler.c",
   "${wifi_sdk_root}/components/device/silabs/si91x/wireless/sl_net/src/sl_si91x_net_credentials.c",
-  "${wifi_sdk_root}/components/device/silabs/si91x/wireless/spi_interface/sl_si91x_spi_driver.c",
+  "${wifi_sdk_root}/components/device/silabs/si91x/wireless/ncp_interface/spi/sl_si91x_spi.c",
+  "${wifi_sdk_root}/components/device/silabs/si91x/wireless/ncp_interface/sl_si91x_ncp_driver.c",
 
   # wifi component
   "${wifi_sdk_root}/components/protocol/wifi/src/sl_wifi_callback_framework.c",

examples/platform/silabs/efr32/wf200/host_if.cpp

@@ -607,7 +607,7 @@ static void wfx_events_task(void * p_arg)
             {
                 // Enable the power save
                 SILABS_LOG("WF200 going to DTIM based sleep");
-                sl_wfx_set_power_mode(WFM_PM_MODE_DTIM, WFM_PM_POLL_FAST_PS, BEACON_1);
+                sl_wfx_set_power_mode(WFM_PM_MODE_DTIM, WFM_PM_POLL_FAST_PS, BEACON_1, 0 /*timeout*/);
                 sl_wfx_enable_device_power_save();
             }
 #endif /* CHIP_CONFIG_ENABLE_ICD_SERVER */

src/platform/silabs/SilabsConfig.cpp

@@ -33,6 +33,7 @@
 #include <nvm3_hal_flash.h>
 #include <nvm3_lock.h>
 
+#ifndef SIWX_917 // 917soc/wifi-sdk implements the same nvm3 lock/unlock mechanism and it currently can't be overide.
 #include <FreeRTOS.h>
 #include <semphr.h>
 // Substitute the GSDK weak nvm3_lockBegin and nvm3_lockEnd
@@ -57,6 +58,7 @@ void nvm3_lockEnd(void)
     VerifyOrDie(nvm3_Sem != NULL);
     xSemaphoreGive(nvm3_Sem);
 }
+#endif // !SIWX_917
 
 namespace chip {
 namespace DeviceLayer {
@@ -76,9 +78,9 @@ CHIP_ERROR SilabsConfig::Init()
 
 void SilabsConfig::DeInit()
 {
-#ifndef BRD4325A // TODO: fix semaphore usage in nvm3_lock for siwx917. use weak implementation for that board instead
+#ifndef SIWX_917
     vSemaphoreDelete(nvm3_Sem);
-#endif // not BRD4325A
+#endif // !SIWX_917
     nvm3_close(nvm3_defaultHandle);
 }
 

third_party/silabs/efr32_sdk.gni

@@ -916,11 +916,11 @@ template("efr32_sdk") {
         "${efr32_sdk_root}/platform/security/sl_component/sl_mbedtls_support/src/crypto_aes.c",
         "${efr32_sdk_root}/platform/security/sl_component/sl_protocol_crypto/src/sli_protocol_crypto_crypto.c",
         "${efr32_sdk_root}/platform/security/sl_component/sl_psa_driver/src/crypto_management.c",
+        "${efr32_sdk_root}/platform/security/sl_component/sl_psa_driver/src/sli_crypto_driver_trng.c",
         "${efr32_sdk_root}/platform/security/sl_component/sl_psa_driver/src/sli_crypto_transparent_driver_aead.c",
         "${efr32_sdk_root}/platform/security/sl_component/sl_psa_driver/src/sli_crypto_transparent_driver_cipher.c",
         "${efr32_sdk_root}/platform/security/sl_component/sl_psa_driver/src/sli_crypto_transparent_driver_hash.c",
         "${efr32_sdk_root}/platform/security/sl_component/sl_psa_driver/src/sli_crypto_transparent_driver_mac.c",
-        "${efr32_sdk_root}/platform/security/sl_component/sl_psa_driver/src/sli_crypto_trng_driver.c",
         "${efr32_sdk_root}/platform/service/device_init/src/sl_device_init_dcdc_s1.c",
         "${efr32_sdk_root}/platform/service/device_init/src/sl_device_init_emu_s1.c",
         "${efr32_sdk_root}/platform/service/device_init/src/sl_device_init_hfxo_s1.c",