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| 1 | +/* |
| 2 | + * (C) Copyright 2005 |
| 3 | + * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 4 | + * |
| 5 | + * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> |
| 6 | + * |
| 7 | + * See file CREDITS for list of people who contributed to this |
| 8 | + * project. |
| 9 | + * |
| 10 | + * This program is free software; you can redistribute it and/or |
| 11 | + * modify it under the terms of the GNU General Public License as |
| 12 | + * published by the Free Software Foundation; either version 2 of |
| 13 | + * the License, or (at your option) any later version. |
| 14 | + * |
| 15 | + * This program is distributed in the hope that it will be useful, |
| 16 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | + * GNU General Public License for more details. |
| 19 | + * |
| 20 | + * You should have received a copy of the GNU General Public License |
| 21 | + * along with this program; if not, write to the Free Software |
| 22 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 23 | + * MA 02111-1307 USA |
| 24 | + */ |
| 25 | + |
| 26 | +#include <ppc_asm.tmpl> |
| 27 | +#include <config.h> |
| 28 | + |
| 29 | +/* General */ |
| 30 | +#define TLB_VALID 0x00000200 |
| 31 | + |
| 32 | +/* Supported page sizes */ |
| 33 | + |
| 34 | +#define SZ_1K 0x00000000 |
| 35 | +#define SZ_4K 0x00000010 |
| 36 | +#define SZ_16K 0x00000020 |
| 37 | +#define SZ_64K 0x00000030 |
| 38 | +#define SZ_256K 0x00000040 |
| 39 | +#define SZ_1M 0x00000050 |
| 40 | +#define SZ_16M 0x00000070 |
| 41 | +#define SZ_256M 0x00000090 |
| 42 | + |
| 43 | +/* Storage attributes */ |
| 44 | +#define SA_W 0x00000800 /* Write-through */ |
| 45 | +#define SA_I 0x00000400 /* Caching inhibited */ |
| 46 | +#define SA_M 0x00000200 /* Memory coherence */ |
| 47 | +#define SA_G 0x00000100 /* Guarded */ |
| 48 | +#define SA_E 0x00000080 /* Endian */ |
| 49 | + |
| 50 | +/* Access control */ |
| 51 | +#define AC_X 0x00000024 /* Execute */ |
| 52 | +#define AC_W 0x00000012 /* Write */ |
| 53 | +#define AC_R 0x00000009 /* Read */ |
| 54 | + |
| 55 | +/* Some handy macros */ |
| 56 | + |
| 57 | +#define EPN(e) ((e) & 0xfffffc00) |
| 58 | +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) |
| 59 | +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) |
| 60 | +#define TLB2(a) ( (a)&0x00000fbf ) |
| 61 | + |
| 62 | +#define tlbtab_start\ |
| 63 | + mflr r1 ;\ |
| 64 | + bl 0f ; |
| 65 | + |
| 66 | +#define tlbtab_end\ |
| 67 | + .long 0, 0, 0 ; \ |
| 68 | +0: mflr r0 ; \ |
| 69 | + mtlr r1 ; \ |
| 70 | + blr ; |
| 71 | + |
| 72 | +#define tlbentry(epn,sz,rpn,erpn,attr)\ |
| 73 | + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) |
| 74 | + |
| 75 | + |
| 76 | +/************************************************************************** |
| 77 | + * TLB TABLE |
| 78 | + * |
| 79 | + * This table is used by the cpu boot code to setup the initial tlb |
| 80 | + * entries. Rather than make broad assumptions in the cpu source tree, |
| 81 | + * this table lets each board set things up however they like. |
| 82 | + * |
| 83 | + * Pointer to the table is returned in r1 |
| 84 | + * |
| 85 | + *************************************************************************/ |
| 86 | + |
| 87 | + .section .bootpg,"ax" |
| 88 | + .globl tlbtab |
| 89 | + |
| 90 | +tlbtab: |
| 91 | + tlbtab_start |
| 92 | + tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) |
| 93 | + tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) |
| 94 | + tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) |
| 95 | + tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) |
| 96 | + tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) |
| 97 | + tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) |
| 98 | + tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) |
| 99 | + tlbtab_end |
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