syncram_8bit.v

// [TURBO9_HEADER_START]
//////////////////////////////////////////////////////////////////////////////
//                          Turbo9 Microprocessor IP
//////////////////////////////////////////////////////////////////////////////
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// Contact: team[at]turbo9[dot]org
//////////////////////////////////////////////////////////////////////////////
// [TURBO9_LICENSE_START]
// BSD-1-Clause
//
// Copyright (c) 2020-2023
// Kevin Phillipson
// Michael Rywalt
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
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// 1. Redistributions of source code must retain the above copyright notice,
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// [TURBO9_LICENSE_END]
//////////////////////////////////////////////////////////////////////////////
// Engineer: Kevin Phillipson
// Description: 8-bit synchronous RAM
//
//////////////////////////////////////////////////////////////////////////////
// History:
// 07.14.2023 - Kevin Phillipson
//   File header added
//
//////////////////////////////////////////////////////////////////////////////
// [TURBO9_HEADER_END]

/////////////////////////////////////////////////////////////////////////////
//                                MODULE
/////////////////////////////////////////////////////////////////////////////
module syncram_8bit
#(
  parameter MEM_ADDR_WIDTH = 12,
  parameter MEM_INIT_FILE = "syncram_8bit.hex"
)
(
  input          CLK_I,
  input          WE_I,
  input   [MEM_ADDR_WIDTH-1:0] ADR_I,
  input   [ 7:0] DAT_I,
  output  [ 7:0] DAT_O
);

/////////////////////////////////////////////////////////////////////////////
//                                LOGIC
/////////////////////////////////////////////////////////////////////////////

reg [7:0] ram [0:(2**MEM_ADDR_WIDTH)-1];
reg [7:0] dat_o_reg;

initial
begin
  $readmemh(MEM_INIT_FILE,ram);
end

always @(posedge CLK_I)
begin
  if (WE_I) begin
    ram[ADR_I] <= DAT_I;
    dat_o_reg  <= DAT_I; //'write first' or transparent mode, less logic in FPGA block rams
  end else begin
    dat_o_reg  <= ram[ADR_I];
  end
end


assign DAT_O = dat_o_reg;

/////////////////////////////////////////////////////////////////////////////

endmodule