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Merge branch 'natevm-bitfield-instructions' into master
2 parents 0d5636c + b5e3ca5 commit 7b220e3

14 files changed

+706
-175
lines changed

source/slang/core.meta.slang

+13
Original file line numberDiff line numberDiff line change
@@ -2716,6 +2716,19 @@ T reinterpret(U value);
27162716

27172717
/// Use an otherwise unused value
27182718
/// This can be used to silence the warning about returning before initializing an out paramter.
2719+
// Bitfield extract / insert
2720+
__generic<T>
2721+
[__readNone]
2722+
[__unsafeForceInlineEarly]
2723+
__intrinsic_op($(kIROp_BitfieldInsert))
2724+
T bitfieldInsert(T base, T insert, int offset, int bits);
2725+
2726+
__generic<T>
2727+
[__readNone]
2728+
[__unsafeForceInlineEarly]
2729+
__intrinsic_op($(kIROp_BitfieldExtract))
2730+
T bitfieldExtract(T value, int offset, int bits);
2731+
27192732
__generic<T>
27202733
[__readNone]
27212734
[ForceInline]

source/slang/glsl.meta.slang

-162
Original file line numberDiff line numberDiff line change
@@ -1150,168 +1150,6 @@ public void imulExtended(highp vector<int,N> x, highp vector<int,N> y, out highp
11501150
}
11511151
}
11521152

1153-
[__readNone]
1154-
[ForceInline]
1155-
[require(cpp_cuda_glsl_hlsl_spirv, GLSL_400)]
1156-
public int bitfieldExtract(int value, int offset, int bits)
1157-
{
1158-
__target_switch
1159-
{
1160-
case glsl: __intrinsic_asm "bitfieldExtract";
1161-
case spirv: return spirv_asm {
1162-
result:$$int = OpBitFieldSExtract $value $offset $bits
1163-
};
1164-
default:
1165-
return int(uint(value >> offset) & ((1u << bits) - 1));
1166-
}
1167-
}
1168-
1169-
__generic<let N:int>
1170-
[__readNone]
1171-
[ForceInline]
1172-
[require(cpp_cuda_glsl_hlsl_spirv, GLSL_400)]
1173-
public vector<int,N> bitfieldExtract(vector<int,N> value, int offset, int bits)
1174-
{
1175-
__target_switch
1176-
{
1177-
case glsl: __intrinsic_asm "bitfieldExtract";
1178-
case spirv: return spirv_asm {
1179-
result:$$vector<int,N> = OpBitFieldSExtract $value $offset $bits
1180-
};
1181-
default:
1182-
vector<int,N> result;
1183-
[ForceUnroll]
1184-
for (int i = 0; i < N; ++i)
1185-
{
1186-
result[i] = bitfieldExtract(value[i], offset, bits);
1187-
}
1188-
return result;
1189-
}
1190-
}
1191-
1192-
[__readNone]
1193-
[ForceInline]
1194-
[require(cpp_cuda_glsl_hlsl_spirv, GLSL_400)]
1195-
public uint bitfieldExtract(uint value, int offset, int bits)
1196-
{
1197-
__target_switch
1198-
{
1199-
case glsl: __intrinsic_asm "bitfieldExtract";
1200-
case spirv: return spirv_asm {
1201-
result:$$uint = OpBitFieldUExtract $value $offset $bits
1202-
};
1203-
default:
1204-
return (value >> offset) & ((1u << bits) - 1);
1205-
}
1206-
}
1207-
1208-
__generic<let N:int>
1209-
[__readNone]
1210-
[ForceInline]
1211-
[require(cpp_cuda_glsl_hlsl_spirv, GLSL_400)]
1212-
public vector<uint,N> bitfieldExtract(vector<uint,N> value, int offset, int bits)
1213-
{
1214-
__target_switch
1215-
{
1216-
case glsl: __intrinsic_asm "bitfieldExtract";
1217-
case spirv: return spirv_asm {
1218-
result:$$vector<uint,N> = OpBitFieldUExtract $value $offset $bits
1219-
};
1220-
default:
1221-
vector<uint,N> result;
1222-
[ForceUnroll]
1223-
for (int i = 0; i < N; ++i)
1224-
{
1225-
result[i] = bitfieldExtract(value[i], offset, bits);
1226-
}
1227-
return result;
1228-
}
1229-
}
1230-
1231-
[__readNone]
1232-
[ForceInline]
1233-
[require(cpp_cuda_glsl_hlsl_spirv, GLSL_400)]
1234-
public uint bitfieldInsert(uint base, uint insert, int offset, int bits)
1235-
{
1236-
__target_switch
1237-
{
1238-
case glsl: __intrinsic_asm "bitfieldInsert";
1239-
case spirv: return spirv_asm {
1240-
result:$$uint = OpBitFieldInsert $base $insert $offset $bits
1241-
};
1242-
default:
1243-
uint clearMask = ~(((1u << bits) - 1u) << offset);
1244-
uint clearedBase = base & clearMask;
1245-
uint maskedInsert = (insert & ((1u << bits) - 1u)) << offset;
1246-
return clearedBase | maskedInsert;
1247-
}
1248-
}
1249-
1250-
__generic<let N:int>
1251-
[__readNone]
1252-
[ForceInline]
1253-
[require(cpp_cuda_glsl_hlsl_spirv, GLSL_400)]
1254-
public vector<uint,N> bitfieldInsert(vector<uint,N> base, vector<uint,N> insert, int offset, int bits)
1255-
{
1256-
__target_switch
1257-
{
1258-
case glsl: __intrinsic_asm "bitfieldInsert";
1259-
case spirv: return spirv_asm {
1260-
result:$$vector<uint,N> = OpBitFieldInsert $base $insert $offset $bits
1261-
};
1262-
default:
1263-
vector<uint,N> result;
1264-
[ForceUnroll]
1265-
for (int i = 0; i < N; ++i)
1266-
{
1267-
result[i] = bitfieldInsert(base[i], insert[i], offset, bits);
1268-
}
1269-
return result;
1270-
}
1271-
}
1272-
1273-
[__readNone]
1274-
[ForceInline]
1275-
[require(cpp_cuda_glsl_hlsl_spirv, GLSL_400)]
1276-
public int bitfieldInsert(int base, int insert, int offset, int bits)
1277-
{
1278-
__target_switch
1279-
{
1280-
case glsl: __intrinsic_asm "bitfieldInsert";
1281-
case spirv: return spirv_asm {
1282-
result:$$int = OpBitFieldInsert $base $insert $offset $bits
1283-
};
1284-
default:
1285-
uint clearMask = ~(((1u << bits) - 1u) << offset);
1286-
uint clearedBase = base & clearMask;
1287-
uint maskedInsert = (insert & ((1u << bits) - 1u)) << offset;
1288-
return clearedBase | maskedInsert;
1289-
}
1290-
}
1291-
1292-
__generic<let N:int>
1293-
[__readNone]
1294-
[ForceInline]
1295-
[require(cpp_cuda_glsl_hlsl_spirv, GLSL_400)]
1296-
public vector<int,N> bitfieldInsert(vector<int,N> base, vector<int,N> insert, int offset, int bits)
1297-
{
1298-
__target_switch
1299-
{
1300-
case glsl: __intrinsic_asm "bitfieldInsert";
1301-
case spirv: return spirv_asm {
1302-
result:$$vector<int,N> = OpBitFieldInsert $base $insert $offset $bits
1303-
};
1304-
default:
1305-
vector<int,N> result;
1306-
[ForceUnroll]
1307-
for (int i = 0; i < N; ++i)
1308-
{
1309-
result[i] = bitfieldInsert(base[i], insert[i], offset, bits);
1310-
}
1311-
return result;
1312-
}
1313-
}
1314-
13151153
[__readNone]
13161154
[ForceInline]
13171155
[require(cpp_cuda_glsl_hlsl_spirv, GLSL_400)]

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