A question on neorv32_tb.simple.vhd

[mahdi259]

Hi
I need to monitor certain memory addresses in testbench and therefore I set tb to use external memories. Is it possible to simulate internal memories by external memories using delay time of 0 for external memories?

[stnolting]

Hey @mahdi259!

I need to monitor certain memory addresses

What is your actual use case? You can monitor all memory transactions by looking at the processor's main bus (right in front of the gateway):

neorv32/rtl/core/neorv32_top.vhd

Lines 741 to 742 in 0949a3e

	req_i => main2_req,
	rsp_o => main2_rsp,

therefore I set tb to use external memories.

So you are using these options?

neorv32/sim/simple/neorv32_tb.simple.vhd

Lines 62 to 63 in 0949a3e

	constant int_imem_c : boolean := true; -- true: use proc-internal IMEM, false: use external simulated IMEM (ext. mem A)
	constant int_dmem_c : boolean := true; -- true: use proc-internal DMEM, false: use external simulated DMEM (ext. mem B)

Is it possible to simulate internal memories by external memories using delay time of 0 for external memories?

I'm not sure what you mean. 🤔 Do you want to use processor-external memories that have the same latency as the processor-internal ones?

[mahdi259]

Hi @stnolting
Thanks for your response.

So you are using these options?

Yes.

I'm not sure what you mean. 🤔 Do you want to use processor-external memories that have the same latency as the processor-internal ones?

I use volatile variables to capture the result of my program. As you guided me previously, I use some VHDL code in testbench file and monitor XBUS transactions and print the data that corresponds to the volatile variable.

This method is only sufficient for external memory. I wondered if it's possible to have internal memory and again print data corresponding to a volatile variable.

According to you, I should use following signals right?

neorv32/rtl/core/neorv32_top.vhd

Lines 741 to 742 in 0949a3e

	req_i => main2_req,
	rsp_o => main2_rsp,

[stnolting]

Ah, I remember. 😅

This method is only sufficient for external memory. I wondered if it's possible to have internal memory and again print data corresponding to a volatile variable.
According to you, I should use following signals right?

That's right. Just add your monitoring logic to main2_req. Here is the type definition:

neorv32/rtl/core/neorv32_package.vhd

Lines 125 to 135 in a9a8e20

	type bus_req_t is record
	addr : std_ulogic_vector(31 downto 0); -- access address
	data : std_ulogic_vector(31 downto 0); -- write data
	ben : std_ulogic_vector(3 downto 0); -- byte enable
	stb : std_ulogic; -- request strobe, single-shot
	rw : std_ulogic; -- 0=read, 1=write
	src : std_ulogic; -- access source (1=instruction fetch, 0=data access)
	priv : std_ulogic; -- set if privileged (machine-mode) access
	rvso : std_ulogic; -- set if reservation set operation (atomic LR/SC)
	fence : std_ulogic; -- set if fence(.i) operation, single-shot, independent of STB
	end record;

[mahdi259]

You are genius!