External DMA Interface

[LukasP46]

Hey all,
I will be implementing an external DMA interface as my next project. I have some questions regarding the naming. To me "DMA" is more a type of memory access than a perephial block. There is already a perephial block named DMA in this project though. How should I name the ports and vhdl files? XDMA? DMA_BUS?

Technically, I'm going to extend the DMA switch to support external bus access and make the priority switchable.

[stnolting]

To me "DMA" is more a type of memory access than a perephial block

I agree. Basically the term "DMA" (= _direct memory access) applies to all device that have direct access to main memory and do not on depend on data being send/read to/from them. So, related to the processor, the CPU itself and the DMA controller have direct memory access while other modules like SLINK or UART need to fed with data from DMA-capable module.

I will be implementing an external DMA interface as my next project.

Can you say something more about this?

Basically, there is already a direct memory interface: the external bus interface. The CPU itself and also the DMA controller have direct access to this interface (in a host role) and thus, can directly access external memory.

[LukasP46]

Can you say something more about this?

I want to be able to add peripherals that can access the memory themselves...

Basically, there is already a direct memory interface: the external bus interface.

... with (optional) priority over the CPU itself. So yes, it is actually just like the external bus interface, but connected to the DMA switch, whose priority can be configured.

This hopefully allows guaranteed access times.

I'm going to choose XDMA as the name for now, but that can of course be adapted later.

[LukasP46]

Okay, here we go. An external interface accessing the entire internal bus might not be a good idea. At least without precautions.

The external master could easily do remote code execution since it could just write to the DMEM. One idea would be to allow only a certain address space, say part of the IMEM and certain IO. But if the stack lands in the IMEM part, we have the same problem, so it should be a part the stack never reaches.

It is also possible to allocate extra memory for the XDMA, so the user only has to define a size and this memory is the only one shared by the processor and the XDMA. But that would make the XDMA obsolete, because you could just use an external memory with an arbiter on its interface. Which might actually be the solution I was looking for in the first place. So thanks for listening and be careful not to open the door too much ;)

[stnolting]

An external interface accessing the entire internal bus might not be a good idea.

Ah, now I understand. We're talking about a device port on the processor side so that an external controller can access internal memories and peripherals.

The external master could easily do remote code execution since it could just write to the DMEM. One idea would be to allow only a certain address space, say part of the IMEM and certain IO. But if the stack lands in the IMEM part, we have the same problem, so it should be a part the stack never reaches.

In "untrsuted" scenarios this would be a real problem. Another solution could be to replciate the physical memory protection logic from the core so that external access requests are also checked.

It is also possible to allocate extra memory for the XDMA, so the user only has to define a size and this memory is the only one shared by the processor and the XDMA. But that would make the XDMA obsolete, because you could just use an external memory with an arbiter on its interface.

Good point. 😅

So thanks for listening and be careful not to open the door too much ;)

But still a worthwhile idea.

[LukasP46]

Another solution could be to replciate the physical memory protection logic from the core so that external access requests are also checked.

I haven't looked into physical memory protection that much, but that might be the way to go if someone needs it :)

But still a worthwhile idea.

Thank you!