Skip to content

Commit 16ab346

Browse files
mathieuchopstmcarlescufi
mathieuchopstm
authored and
carlescufi
committed
soc: st: stm32: add STM32WB0 series
Adds support for the STM32WB0 MCU series. Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
1 parent 4670c3c commit 16ab346

File tree

9 files changed

+302
-0
lines changed

9 files changed

+302
-0
lines changed

‎soc/st/stm32/common/soc_config.c

+5
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@
1414
#include <zephyr/arch/cpu.h>
1515
#include <stm32_ll_system.h>
1616
#include <stm32_ll_bus.h>
17+
#include <stm32_ll_pwr.h>
1718

1819
/**
1920
* @brief Perform SoC configuration at boot.
@@ -80,6 +81,8 @@ static int st_stm32_common_config(void)
8081
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_DBGMCU);
8182
LL_DBGMCU_EnableDBGStopMode();
8283
LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_DBGMCU);
84+
#elif defined(CONFIG_SOC_SERIES_STM32WB0X)
85+
LL_PWR_EnableDEEPSTOP2();
8386
#else /* all other parts */
8487
LL_DBGMCU_EnableDBGStopMode();
8588
#endif
@@ -102,6 +105,8 @@ static int st_stm32_common_config(void)
102105
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_DBGMCU);
103106
LL_DBGMCU_DisableDBGStopMode();
104107
LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_DBGMCU);
108+
#elif defined(CONFIG_SOC_SERIES_STM32WB0X)
109+
LL_PWR_DisableDEEPSTOP2();
105110
#else /* all other parts */
106111
LL_DBGMCU_DisableDBGStopMode();
107112
#endif

‎soc/st/stm32/soc.yml

+6
Original file line numberDiff line numberDiff line change
@@ -197,6 +197,12 @@ family:
197197
- name: stm32wbx
198198
socs:
199199
- name: stm32wb55xx
200+
- name: stm32wb0x
201+
socs:
202+
- name: stm32wb05
203+
- name: stm32wb06
204+
- name: stm32wb07
205+
- name: stm32wb09
200206
- name: stm32wbax
201207
socs:
202208
- name: stm32wba52xx

‎soc/st/stm32/stm32wb0x/CMakeLists.txt

+10
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
# SPDX-License-Identifier: Apache-2.0
2+
3+
zephyr_include_directories(${ZEPHYR_BASE}/drivers)
4+
5+
zephyr_sources(soc.c)
6+
zephyr_include_directories(.)
7+
8+
zephyr_linker_sources(RAM_SECTIONS ram_sections.ld)
9+
10+
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

‎soc/st/stm32/stm32wb0x/Kconfig

+15
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
# STMicroelectronics STM32W0 MCU series
2+
3+
# Copyright (c) 2024 STMicroelectronics
4+
# SPDX-License-Identifier: Apache-2.0
5+
6+
config SOC_SERIES_STM32WB0X
7+
select ARM
8+
select CPU_CORTEX_M0PLUS
9+
select CPU_CORTEX_M_HAS_VTOR
10+
select CPU_CORTEX_M_HAS_SYSTICK
11+
select CPU_HAS_ARM_MPU
12+
select HAS_STM32CUBE
13+
# WB0x has a ROM bootloader executed at reset,
14+
# which makes the following option required
15+
select INIT_ARCH_HW_AT_BOOT

‎soc/st/stm32/stm32wb0x/Kconfig.defconfig

+11
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
# STMicroelectronics STM32WB0 MCU series
2+
3+
# Copyright (c) 2024 STMicroelectronics
4+
# SPDX-License-Identifier: Apache-2.0
5+
6+
if SOC_SERIES_STM32WB0X
7+
8+
config NUM_IRQS
9+
default 32
10+
11+
endif # SOC_SERIES_STM32WB0X

‎soc/st/stm32/stm32wb0x/Kconfig.soc

+33
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,33 @@
1+
# STMicroelectronics STM32WB0 MCU series
2+
3+
# Copyright (c) 2024 STMicroelectronics
4+
# SPDX-License-Identifier: Apache-2.0
5+
6+
config SOC_SERIES_STM32WB0X
7+
bool
8+
select SOC_FAMILY_STM32
9+
10+
config SOC_SERIES
11+
default "stm32wb0x" if SOC_SERIES_STM32WB0X
12+
13+
config SOC_STM32WB05XX
14+
bool
15+
select SOC_SERIES_STM32WB0X
16+
17+
config SOC_STM32WB06XX
18+
bool
19+
select SOC_SERIES_STM32WB0X
20+
21+
config SOC_STM32WB07XX
22+
bool
23+
select SOC_SERIES_STM32WB0X
24+
25+
config SOC_STM32WB09XX
26+
bool
27+
select SOC_SERIES_STM32WB0X
28+
29+
config SOC
30+
default "stm32wb05" if SOC_STM32WB05XX
31+
default "stm32wb06" if SOC_STM32WB06XX
32+
default "stm32wb07" if SOC_STM32WB07XX
33+
default "stm32wb09" if SOC_STM32WB09XX

‎soc/st/stm32/stm32wb0x/ram_sections.ld

+22
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,22 @@
1+
/*
2+
* Copyright (c) 2024 STMicroelectronics
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
/** Refer to `soc.c` for more information about these areas. */
8+
SECTION_PROLOGUE(stm32wb0_RAM_VR, 0x20000000 (NOLOAD), )
9+
{
10+
/* For historical reasons, leave the first word of
11+
* SRAM0 unused, even though it could store data.
12+
* The structure MUST start at address 0x2000_0004.
13+
*/
14+
. += 4;
15+
16+
KEEP(*(stm32wb0_RAM_VR));
17+
} GROUP_LINK_IN(RAMABLE_REGION)
18+
19+
SECTION_PROLOGUE(stm32wb0_BLUE_RAM, 0x200000C0 (NOLOAD), )
20+
{
21+
KEEP(*(stm32wb0_BLUE_RAM));
22+
} GROUP_LINK_IN(RAMABLE_REGION)

‎soc/st/stm32/stm32wb0x/soc.c

+178
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,178 @@
1+
/*
2+
* Copyright (c) 2024 STMicroelectronics
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
/**
8+
* @file
9+
* @brief System/hardware module for STM32WB0 processor
10+
*/
11+
12+
#include <zephyr/device.h>
13+
#include <zephyr/init.h>
14+
#include <stm32_ll_bus.h>
15+
#include <stm32_ll_pwr.h>
16+
#include <stm32_ll_system.h>
17+
#include <stm32_ll_radio.h>
18+
#include <zephyr/logging/log.h>
19+
#include <zephyr/toolchain.h>
20+
#include <cmsis_core.h>
21+
#include <stdint.h>
22+
23+
#include <system_stm32wb0x.h>
24+
25+
#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
26+
LOG_MODULE_REGISTER(soc);
27+
28+
/**
29+
* CMSIS System Core Clock: global variable holding the system core clock,
30+
* which is the frequency supplied to the SysTick timer and processor core.
31+
*
32+
* On STM32WB0 series, after RESET, the system clock frequency is 16MHz.
33+
*/
34+
uint32_t SystemCoreClock = 16000000U;
35+
36+
/**
37+
* RAM Virtual Register: special structure located at the start
38+
* of SRAM0; used by the UART bootloader and the Low Power Manager.
39+
* Data type definition comes from @ref system_stm32wb0xx.h
40+
*/
41+
Z_GENERIC_SECTION("stm32wb0_RAM_VR")
42+
__used RAM_VR_TypeDef RAM_VR;
43+
44+
/** Power Controller node */
45+
#define PWRC DT_INST(0, st_stm32wb0_pwr)
46+
47+
/** SMPS modes */
48+
#define STM32WB0_SMPS_MODE_OFF 0
49+
#define STM32WB0_SMPS_MODE_PRECHARGE 1
50+
#define STM32WB0_SMPS_MODE_RUN 2
51+
52+
#define SMPS_MODE _CONCAT(STM32WB0_SMPS_MODE_, DT_STRING_UNQUOTED(PWRC, smps_mode))
53+
54+
/* Convert DTS properties to LL macros */
55+
#define SMPS_PRESCALER _CONCAT(LL_RCC_SMPS_DIV_, DT_PROP(PWRC, smps_clock_prescaler))
56+
57+
#if SMPS_MODE != STM32WB0_SMPS_MODE_OFF
58+
BUILD_ASSERT(DT_NODE_HAS_PROP(PWRC, smps_bom),
59+
"smps-bom must be specified");
60+
61+
#define SMPS_BOM \
62+
_CONCAT(LL_PWR_SMPS_BOM, DT_PROP(PWRC, smps_bom))
63+
64+
#define SMPS_LP_MODE \
65+
COND_CODE_1( \
66+
DT_PROP(PWRC, smps_lp_floating), \
67+
(LL_PWR_SMPS_LPOPEN), \
68+
(LL_PWR_NO_SMPS_LPOPEN))
69+
70+
#define SMPS_CURRENT_LIMIT \
71+
_CONCAT(LL_PWR_SMPS_PRECH_LIMIT_CUR_, \
72+
DT_STRING_UNQUOTED(PWRC, smps_current_limit))
73+
74+
#define SMPS_OUTPUT_VOLTAGE \
75+
_CONCAT(LL_PWR_SMPS_OUTPUT_VOLTAGE_, \
76+
DT_STRING_UNQUOTED(PWRC, smps_output_voltage))
77+
#endif /* SMPS_MODE != STM32WB0_SMPS_MODE_OFF */
78+
79+
static void configure_smps(void)
80+
{
81+
/* Configure SMPS clock prescaler */
82+
LL_RCC_SetSMPSPrescaler(SMPS_PRESCALER);
83+
84+
#if SMPS_MODE == STM32WB0_SMPS_MODE_OFF
85+
/* Disable SMPS */
86+
LL_PWR_SetSMPSMode(LL_PWR_NO_SMPS);
87+
88+
while (LL_PWR_IsSMPSReady()) {
89+
/* Wait for SMPS to turn off */
90+
}
91+
#else
92+
/* Select correct BOM */
93+
LL_PWR_SetSMPSBOM(SMPS_BOM);
94+
95+
/* Configure low-power mode */
96+
LL_PWR_SetSMPSOpenMode(SMPS_LP_MODE);
97+
98+
/* Enable SMPS */
99+
LL_PWR_SetSMPSMode(LL_PWR_SMPS);
100+
101+
while (!LL_PWR_IsSMPSReady()) {
102+
/* Wait for SMPS to turn on */
103+
}
104+
105+
/* Place SMPS in PRECHARGE (BYPASS) mode.
106+
* This is required to change SMPS output voltage,
107+
* so we can do it unconditionally.
108+
*/
109+
LL_PWR_SetSMPSPrechargeMode(LL_PWR_SMPS_PRECHARGE);
110+
while (LL_PWR_IsSMPSinRUNMode()) {
111+
/* Wait for SMPS to enter PRECHARGE mode */
112+
}
113+
114+
if (SMPS_MODE == STM32WB0_SMPS_MODE_PRECHARGE) {
115+
/**
116+
* SMPS should remain in PRECHARGE mode, but
117+
* we still have to configure the current limit.
118+
*/
119+
LL_PWR_SetSMPSPrechargeLimitCurrent(SMPS_CURRENT_LIMIT);
120+
} else {
121+
/**
122+
* SMPS mode requested is RUN mode. Configure the output
123+
* voltage to the desired value then exit PRECHARGE mode.
124+
*/
125+
LL_PWR_SMPS_SetOutputVoltageLevel(SMPS_OUTPUT_VOLTAGE);
126+
127+
/* Exit PRECHARGE mode (returns in RUN mode) */
128+
LL_PWR_SetSMPSPrechargeMode(LL_PWR_NO_SMPS_PRECHARGE);
129+
while (!LL_PWR_IsSMPSinRUNMode()) {
130+
/* Wait for SMPS to enter RUN mode */
131+
}
132+
}
133+
#endif /* SMPS_MODE == STM32WB0_SMPS_MODE_OFF */
134+
}
135+
136+
/**
137+
* @brief Perform basic hardware initialization at boot.
138+
*
139+
* This needs to be run from the very beginning,
140+
* so the init priority has to be 0 (zero).
141+
*
142+
* @return 0
143+
*/
144+
static int stm32wb0_init(void)
145+
{
146+
/* Update CMSIS SystemCoreClock variable (CLK_SYS) */
147+
/* On reset, the 64MHz HSI is selected as input to
148+
* the SYSCLKPRE prescaler, set to 4, resulting in
149+
* CLK_SYS being equal to 16MHz.
150+
*/
151+
SystemCoreClock = 16000000U;
152+
153+
/* Remap address 0 to user flash memory */
154+
LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_FLASH);
155+
156+
/**
157+
* Save application exception vector address in RAM_VR.
158+
* By now, SCB->VTOR should point to _vector_table,
159+
* so use that value instead of _vector_table directly.
160+
*/
161+
RAM_VR.AppBase = SCB->VTOR;
162+
163+
/* Enable retention of all RAM banks in Deepstop */
164+
LL_PWR_EnableRAMBankRet(LL_PWR_RAMRET_1);
165+
#if defined(LL_PWR_RAMRET_2)
166+
LL_PWR_EnableRAMBankRet(LL_PWR_RAMRET_2);
167+
#endif
168+
#if defined(LL_PWR_RAMRET_3)
169+
LL_PWR_EnableRAMBankRet(LL_PWR_RAMRET_3);
170+
#endif
171+
172+
/* Configure SMPS step-down converter */
173+
configure_smps();
174+
175+
return 0;
176+
}
177+
178+
SYS_INIT(stm32wb0_init, PRE_KERNEL_1, 0);

‎soc/st/stm32/stm32wb0x/soc.h

+22
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,22 @@
1+
/*
2+
* Copyright (c) 2024 STMicroelectronics
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
/**
8+
* @file SoC configuration macros for the STM32WB0 family processors.
9+
*
10+
*/
11+
12+
13+
#ifndef _STM32WB0_SOC_H_
14+
#define _STM32WB0_SOC_H_
15+
16+
#ifndef _ASMLANGUAGE
17+
18+
#include <stm32wb0x.h>
19+
20+
#endif /* !_ASMLANGUAGE */
21+
22+
#endif /* _STM32WB0_SOC_H_ */

0 commit comments

Comments
 (0)