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mathieuchopstmcarlescufi
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drivers: intc: add STM32WB0 GPIO interrupt controller
Adds a driver for the STM32WB0 series GPIO interrupt controller. This driver implements the STM32 GPIO INTC API, along with an extension function used to check if a specific line is available on current board. This also extends the GPIO INTC API to support level-sensitive interrupts, as this feature is available on STM32WB0. Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
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‎drivers/interrupt_controller/CMakeLists.txt

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Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@ zephyr_library_sources_ifdef(CONFIG_GIC_V1 intc_gic.c)
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zephyr_library_sources_ifdef(CONFIG_GIC_V2 intc_gic.c)
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zephyr_library_sources_ifdef(CONFIG_GIC_V3 intc_gicv3.c)
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zephyr_library_sources_ifdef(CONFIG_GIC_V3_ITS intc_gicv3_its.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_INTC_STM32WB0 intc_gpio_stm32wb0.c)
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zephyr_library_sources_ifdef(CONFIG_INTEL_VTD_ICTL intc_intel_vtd.c)
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zephyr_library_sources_ifdef(CONFIG_IOAPIC intc_ioapic.c)
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zephyr_library_sources_ifdef(CONFIG_ITE_IT8XXX2_INTC intc_ite_it8xxx2.c)

‎drivers/interrupt_controller/Kconfig.stm32

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Original file line numberDiff line numberDiff line change
@@ -12,4 +12,11 @@ config EXTI_STM32
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help
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Enable EXTI driver for STM32 line of MCUs
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config GPIO_INTC_STM32WB0
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bool "GPIO Interrupt Controller Driver for STM32WB0 series"
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default y
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depends on DT_HAS_ST_STM32WB0_GPIO_INTC_ENABLED
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help
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Enable GPIO interrupt controller driver for STM32WB0 series
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endif # SOC_FAMILY_STM32

‎drivers/interrupt_controller/intc_gpio_stm32wb0.c

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@@ -0,0 +1,295 @@
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/*
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* Copyright (c) 2024 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief Driver for STM32WB0 GPIO interrupt controller
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*
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* In this file, "EXTI" should be understood as "GPIO interrupt controller".
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* There is no "External interrupt/event controller (EXTI)" in STM32WB0 MCUs.
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*/
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#define DT_DRV_COMPAT st_stm32wb0_gpio_intc
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#include <errno.h>
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#include <soc.h>
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#include <stm32_ll_system.h>
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#include <zephyr/irq.h>
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#include <zephyr/device.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/sys/__assert.h>
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#include <zephyr/drivers/interrupt_controller/gpio_intc_stm32.h>
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#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl-common.h> /* For PORTA/PORTB defines */
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#define INTC_NODE DT_DRV_INST(0)
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#define NUM_GPIO_PORTS (2)
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#define NUM_PINS_PER_GPIO_PORT (16)
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#define GPIO_PORT_TABLE_INDEX(port) \
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DT_PROP_BY_IDX(INTC_NODE, line_ranges, UTIL_X2(port))
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/* For good measure only */
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#define _NUM_GPIOS_ON_PORT_X(x) \
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DT_PROP_BY_IDX(INTC_NODE, line_ranges, UTIL_INC(UTIL_X2(x)))
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BUILD_ASSERT(DT_PROP_LEN(INTC_NODE, line_ranges) == (2 * NUM_GPIO_PORTS));
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BUILD_ASSERT(_NUM_GPIOS_ON_PORT_X(STM32_PORTA) == NUM_PINS_PER_GPIO_PORT);
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BUILD_ASSERT(_NUM_GPIOS_ON_PORT_X(STM32_PORTB) == NUM_PINS_PER_GPIO_PORT);
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BUILD_ASSERT(GPIO_PORT_TABLE_INDEX(STM32_PORTB) == NUM_PINS_PER_GPIO_PORT);
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#undef _NUM_GPIOS_ON_PORT_X
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/* wrapper for user callback */
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struct gpio_irq_cb_wrp {
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stm32_gpio_irq_cb_t fn;
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void *data;
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};
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/* wrapper for ISR argument block */
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struct wb0_gpio_isr_argblock {
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/* LL define for first line on GPIO port
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* (= least significant bit of the port's defines)
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*/
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uint32_t port_first_line;
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/* Pointer to first element of irq_callbacks_table
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* array that corresponds to this GPIO line
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*/
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struct gpio_irq_cb_wrp *cb_table;
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};
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/* driver data */
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struct stm32wb0_gpio_intc_data {
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/* per-port user callbacks */
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struct gpio_irq_cb_wrp irq_cb_table[
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NUM_GPIO_PORTS * NUM_PINS_PER_GPIO_PORT];
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};
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/**
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* @returns the LL_EXTI_LINE_Pxy define for pin @p pin on GPIO port @p port
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*/
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static inline stm32_gpio_irq_line_t portpin_to_ll_exti_line(uint32_t port, gpio_pin_t pin)
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{
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stm32_gpio_irq_line_t line = (1U << pin);
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if (port == STM32_PORTB) {
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line <<= SYSCFG_IO_DTR_PB0_DT_Pos;
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} else if (port == STM32_PORTA) {
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line <<= SYSCFG_IO_DTR_PA0_DT_Pos;
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} else {
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__ASSERT_NO_MSG(0);
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}
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return line;
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}
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/**
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* @returns a 32-bit value contaning:
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* - <5:5> port number (0 = PORTA, 1 = PORTB)
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* - <4:0> pin number (0~15)
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*
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* The returned value is always between 0~31.
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*/
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static inline uint32_t ll_exti_line_to_portpin(stm32_gpio_irq_line_t line)
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{
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return LOG2(line);
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}
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/**
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* @brief Retrieves the user callback block for a given line
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*/
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static struct gpio_irq_cb_wrp *irq_cb_wrp_for_line(stm32_gpio_irq_line_t line)
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{
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const struct device *const dev = DEVICE_DT_GET(INTC_NODE);
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struct stm32wb0_gpio_intc_data *const data = dev->data;
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const uint32_t index = ll_exti_line_to_portpin(line);
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return data->irq_cb_table + index;
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}
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/* Interrupt subroutines */
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static void stm32wb0_gpio_isr(const void *userdata)
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{
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const struct wb0_gpio_isr_argblock *arg = userdata;
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const struct gpio_irq_cb_wrp *cb_table = arg->cb_table;
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uint32_t line = arg->port_first_line;
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for (uint32_t i = 0; i < NUM_PINS_PER_GPIO_PORT; i++, line <<= 1) {
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if (LL_EXTI_IsActiveFlag(line) != 0) {
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/* clear pending interrupt */
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LL_EXTI_ClearFlag(line);
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/* execute user callback if registered */
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if (cb_table[i].fn != NULL) {
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const gpio_port_pins_t pin = (1U << i);
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cb_table[i].fn(pin, cb_table[i].data);
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}
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}
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}
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}
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/**
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* Define the driver data early so that the macro that follows can
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* refer to it directly instead of indirecting through drv->data.
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*/
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static struct stm32wb0_gpio_intc_data gpio_intc_data;
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/**
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* This macro creates the ISR argument block for the @p pidx GPIO port,
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* connects the ISR to the interrupt line and enable IRQ at NVIC level.
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*
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* @param node GPIO INTC device tree node
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* @param pidx GPIO port index
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* @param plin LL define of first line on GPIO port
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*/
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#define INIT_INTC_PORT_INNER(node, pidx, plin) \
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static const struct wb0_gpio_isr_argblock \
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port ##pidx ##_argblock = { \
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.port_first_line = plin, \
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.cb_table = gpio_intc_data.irq_cb_table + \
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GPIO_PORT_TABLE_INDEX(pidx) \
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}; \
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\
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IRQ_CONNECT(DT_IRQN_BY_IDX(node, pidx), \
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DT_IRQ_BY_IDX(node, pidx, priority), \
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stm32wb0_gpio_isr, &port ##pidx ##_argblock, 0); \
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\
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irq_enable(DT_IRQN_BY_IDX(node, pidx))
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#define STM32WB0_INIT_INTC_FOR_PORT(_PORT) \
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INIT_INTC_PORT_INNER(INTC_NODE, \
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STM32_PORT ##_PORT, LL_EXTI_LINE_P ##_PORT ## 0)
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/**
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* @brief Initializes the GPIO interrupt controller driver
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*/
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static int stm32wb0_gpio_intc_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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STM32WB0_INIT_INTC_FOR_PORT(A);
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STM32WB0_INIT_INTC_FOR_PORT(B);
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return 0;
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}
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DEVICE_DT_DEFINE(INTC_NODE, &stm32wb0_gpio_intc_init,
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NULL, &gpio_intc_data, NULL, PRE_KERNEL_1,
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CONFIG_INTC_INIT_PRIORITY, NULL);
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/**
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* @brief STM32 GPIO interrupt controller API implementation
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*/
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/**
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* @internal
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* STM32WB0 GPIO interrupt controller driver:
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* The type @ref stm32_gpio_irq_line_t is used to hold the LL_EXTI_LINE_Pxy
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* defines that corresponds to the specified pin. Note that these defines
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* also contain the target GPIO port.
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* @endinternal
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*/
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stm32_gpio_irq_line_t stm32_gpio_intc_get_pin_irq_line(uint32_t port, gpio_pin_t pin)
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{
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return portpin_to_ll_exti_line(port, pin);
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}
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void stm32_gpio_intc_enable_line(stm32_gpio_irq_line_t line)
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{
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/* Enable line interrupt at INTC level */
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LL_EXTI_EnableIT(line);
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/**
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* Nothing else to do; INTC interrupt line
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* is enabled at NVIC level during init.
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*/
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}
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void stm32_gpio_intc_disable_line(stm32_gpio_irq_line_t line)
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{
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/* Disable line interrupt at INTC level */
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LL_EXTI_DisableIT(line);
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}
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void stm32_gpio_intc_select_line_trigger(stm32_gpio_irq_line_t line, uint32_t trg)
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{
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switch (trg) {
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case STM32_GPIO_IRQ_TRIG_NONE:
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/**
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* There is no NONE trigger on STM32WB0.
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* We could disable the line interrupts here, but it isn't
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* really necessary: the GPIO driver already does it by
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* calling @ref stm32_gpio_intc_disable_line before calling
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* us with @p trigger = STM32_EXTI_TRIG_NONE.
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*/
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break;
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case STM32_GPIO_IRQ_TRIG_RISING:
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LL_EXTI_EnableEdgeDetection(line);
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LL_EXTI_DisableBothEdgeTrig(line);
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LL_EXTI_EnableRisingTrig(line);
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break;
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case STM32_GPIO_IRQ_TRIG_FALLING:
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LL_EXTI_EnableEdgeDetection(line);
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LL_EXTI_DisableBothEdgeTrig(line);
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LL_EXTI_DisableRisingTrig(line);
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break;
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case STM32_GPIO_IRQ_TRIG_BOTH:
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LL_EXTI_EnableEdgeDetection(line);
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LL_EXTI_EnableBothEdgeTrig(line);
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break;
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case STM32_GPIO_IRQ_TRIG_HIGH_LEVEL:
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LL_EXTI_DisableEdgeDetection(line);
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LL_EXTI_EnableRisingTrig(line);
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break;
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case STM32_GPIO_IRQ_TRIG_LOW_LEVEL:
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LL_EXTI_DisableEdgeDetection(line);
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LL_EXTI_DisableRisingTrig(line);
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break;
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default:
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__ASSERT_NO_MSG(0);
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break;
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}
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/* Since it is not possible to disable triggers on STM32WB0,
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* unlike in other STM32 series, activity on GPIO pin may have
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* set the "event occurred" bit spuriously.
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*
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* Clear the bit now after reconfiguration to make sure that no
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* spurious interrupt is delivered. (This works because interrupts
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* are enabled *after* trigger selection by the GPIO driver, which
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* is the only sensical order to do things in)
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*/
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LL_EXTI_ClearFlag(line);
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}
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int stm32_gpio_intc_set_irq_callback(stm32_gpio_irq_line_t line,
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stm32_gpio_irq_cb_t cb, void *data)
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{
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struct gpio_irq_cb_wrp *cb_wrp = irq_cb_wrp_for_line(line);
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if ((cb_wrp->fn == cb) && (cb_wrp->data == data)) {
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return 0;
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}
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/* If line already has a callback, return EBUSY */
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if (cb_wrp->fn != NULL) {
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return -EBUSY;
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}
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cb_wrp->fn = cb;
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cb_wrp->data = data;
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return 0;
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}
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void stm32_gpio_intc_remove_irq_callback(uint32_t line)
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{
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struct gpio_irq_cb_wrp *cb_wrp = irq_cb_wrp_for_line(line);
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cb_wrp->fn = cb_wrp->data = NULL;
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}

‎include/zephyr/drivers/interrupt_controller/gpio_intc_stm32.h

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@@ -55,6 +55,10 @@ enum stm32_gpio_irq_trigger {
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STM32_GPIO_IRQ_TRIG_FALLING = 0x2,
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/* Trigger on both rising and falling edge */
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STM32_GPIO_IRQ_TRIG_BOTH = 0x3,
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/* Trigger on high level */
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STM32_GPIO_IRQ_TRIG_HIGH_LEVEL = 0x4,
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/* Trigger on low level */
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STM32_GPIO_IRQ_TRIG_LOW_LEVEL = 0x5
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};
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/**

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