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telink: tl3218x: add retention mode (#469)
 - fix the compilation error of gpio . - adjust the RAM distribution of retention . - update the lib of PM mode . Signed-off-by: Fengtai Xie <fengtai.xie@telink-semi.com>
1 parent 930b6d4 commit 9e39d9f

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9 files changed

+50
-26
lines changed

9 files changed

+50
-26
lines changed

‎.github/workflows/telink-tl321x-build.yaml

+12
Original file line numberDiff line numberDiff line change
@@ -107,6 +107,16 @@ jobs:
107107
cd ..
108108
west build -b tl3218x -d build_usb_console_tl321x zephyr/samples/subsys/usb/console -- -DCONFIG_COMPILER_WARNINGS_AS_ERRORS=y
109109
110+
- name: Build TL321X boards/telink/tl321x/basic
111+
run: |
112+
cd ..
113+
west build -b tl3218x_retention -d build_retention_basic_tl321x zephyr/samples/boards/tlsr9x/basic -- -DCONFIG_COMPILER_WARNINGS_AS_ERRORS=y -DCONFIG_SOC_SERIES_RISCV_TELINK_TLX_NON_RETENTION_RAM_CODE=y
114+
115+
- name: Build TL321X net/sockets/echo_client for OpenThread with PM deep-sleep
116+
run: |
117+
cd ..
118+
west build -b tl3218x_retention -d build_ot_echo_client_pm_deep_tl321x zephyr/samples/net/sockets/echo_client -- -DCONFIG_COMPILER_WARNINGS_AS_ERRORS=y -DOVERLAY_CONFIG=overlay-ot-sed.conf -DCONFIG_OPENTHREAD_NETWORKKEY=\"09:24:01:56:04:4a:45:0b:23:22:1e:0e:3b:0d:0e:61:2f:1b:2c:24\" -DCONFIG_PM=y -DCONFIG_SOC_SERIES_RISCV_TELINK_TLX_NON_RETENTION_RAM_CODE=y -DCONFIG_TELINK_TLX_2_WIRE_SPI_ENABLE=y
119+
110120
- name: Build TL321X crypto/mbedtls
111121
run: |
112122
cd ..
@@ -138,6 +148,8 @@ jobs:
138148
cp ../build_ot_cli_tl321x/zephyr/zephyr.bin telink_build_artifacts/tl321x_ot_cli.bin
139149
cp ../build_ot_coprocessor_rcp_uart_tl321x/zephyr/zephyr.bin telink_build_artifacts/tl321x_ot_coprocessor_rcp_uart.bin
140150
cp ../build_usb_console_tl321x/zephyr/zephyr.bin telink_build_artifacts/tl321x_usb_console.bin
151+
cp ../build_retention_basic_tl321x/zephyr/zephyr.bin telink_build_artifacts/tl321x_retention_basic.bin
152+
cp ../build_ot_echo_client_pm_deep_tl321x/zephyr/zephyr.bin telink_build_artifacts/tl321x_ot_echo_client_pm_retention.bin
141153
cp ../build_crypto_mbedtls_tl321x/zephyr/zephyr.bin telink_build_artifacts/tl321x_mbedtls.bin
142154
cp ../build_mcuboot_chip_id_tl321x/zephyr/zephyr.bin telink_build_artifacts/tl321x_mcuboot_chip_id.bin
143155

‎.github/workflows/telink-tl721x-build.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -151,7 +151,7 @@ jobs:
151151
cp ../build_ot_echo_client_pm_deep_tl721x/zephyr/zephyr.bin telink_build_artifacts/tl721x_ot_echo_client_pm_retention.bin
152152
cp ../build_crypto_mbedtls_tl721x/zephyr/zephyr.bin telink_build_artifacts/tl721x_mbedtls.bin
153153
cp ../build_spi_flash_tl721x/zephyr/zephyr.bin telink_build_artifacts/tl721x_spi_flash.bin
154-
cp ../build_mcuboot_chip_id_tl721x/zephyr/zephyr.bin telink_build_artifacts/tl721x_mcuboot_chip_id.bin
154+
cp ../build_mcuboot_chip_id_tl721x/zephyr/zephyr.bin telink_build_artifacts/tl721x_mcuboot_chip_id.bin
155155
156156
- name: Publish artifacts
157157
uses: actions/upload-artifact@v4

‎boards/telink/tl321x/tl3218x_retention.dts

+6-5
Original file line numberDiff line numberDiff line change
@@ -11,13 +11,14 @@
1111
/ {
1212
soc {
1313

14-
/delete-node/ memory@0;
14+
/delete-node/ memory@68000;
15+
/delete-node/ memory@80000;
1516

16-
ram_ilm_retention: memory@0 {
17+
ram_ilm_retention: memory@68000 {
1718
compatible = "mmio-sram";
1819
};
1920

20-
ram_ilm_nonretention: memory@18000 {
21+
ram_ilm_nonretention: memory@80000 {
2122
compatible = "mmio-sram";
2223
};
2324
};
@@ -43,9 +44,9 @@
4344
};
4445

4546
&ram_ilm_retention {
46-
reg = <0x00000000 0x00018000>;
47+
reg = <0x00068000 0x00018000>;
4748
};
4849

4950
&ram_ilm_nonretention {
50-
reg = <0x00018000 0x00028000>;
51+
reg = <0x00080000 0x00008000>;
5152
};

‎drivers/gpio/gpio_tlx.c

+13-12
Original file line numberDiff line numberDiff line change
@@ -76,7 +76,7 @@
7676
#define PIN_NUM_MAX ((uint8_t)7u)
7777

7878
/* IRQ Enable registers */
79-
#if CONFIG_SOC_RISCV_TELINK_TL721X
79+
#if CONFIG_SOC_RISCV_TELINK_TL721X || CONFIG_SOC_RISCV_TELINK_TL321X
8080
#define reg_irq_risc0_en(i) REG_ADDR8(0x140c08 + (i << 4))
8181
#define reg_irq_risc1_en(i) REG_ADDR8(0x140c09 + (i << 4))
8282
#endif
@@ -107,9 +107,7 @@
107107
#if CONFIG_SOC_RISCV_TELINK_TL721X
108108
#define IRQ_GPIO2_RISC0 ((uint8_t)26u)
109109
#define IRQ_GPIO2_RISC1 ((uint8_t)27u)
110-
#endif
111-
112-
#if CONFIG_SOC_RISCV_TELINK_TL721X || CONFIG_SOC_RISCV_TELINK_TL321X
110+
#elif CONFIG_SOC_RISCV_TELINK_TL321X
113111
#define IRQ_GPIO0 ((uint8_t)34u)
114112
#define IRQ_GPIO1 ((uint8_t)35u)
115113
#define IRQ_GPIO2 ((uint8_t)36u)
@@ -118,6 +116,9 @@
118116
#define IRQ_GPIO5 ((uint8_t)39u)
119117
#define IRQ_GPIO6 ((uint8_t)40u)
120118
#define IRQ_GPIO7 ((uint8_t)41u)
119+
#define IRQ_GPIO IRQ_GPIO0
120+
#define IRQ_GPIO2_RISC0 IRQ_GPIO1
121+
#define IRQ_GPIO2_RISC1 IRQ_GPIO2
121122
#endif
122123

123124
/* tlx GPIO registers structure */
@@ -786,7 +787,7 @@ static int gpio_tlx_pm_action(const struct device *dev, enum pm_device_action ac
786787
analog_write_reg8(areg_gpio_pc_ie,
787788
data->gpio_tlx_retention.analog_in_conf);
788789
#if CONFIG_SOC_RISCV_TELINK_TL321X
789-
} else if (IS_PORT_B(gpio) && ((pin >= 4) && (pin <= 7))) {
790+
} else if (IS_PORT_B(gpio)) {
790791
analog_write_reg8(areg_gpio_pb_ie,
791792
data->gpio_tlx_retention.analog_in_conf);
792793
#elif CONFIG_SOC_RISCV_TELINK_TL721X
@@ -820,22 +821,22 @@ static int gpio_tlx_pm_action(const struct device *dev, enum pm_device_action ac
820821
* pending bit and restoring the edge mode
821822
*/
822823
if (irq_num == IRQ_GPIO) {
823-
BM_SET(GPIO_IRQ_REG, FLD_GPIO_IRQ_LVL_GPIO);
824+
BM_SET(GPIO_IRQ_REG, FLD_GPIO_CORE_INTERRUPT_EN);
824825
} else if (irq_num == IRQ_GPIO2_RISC0) {
825-
BM_SET(GPIO_IRQ_REG, FLD_GPIO_IRQ_LVL_GPIO2RISC0);
826+
BM_SET(GPIO_IRQ_REG, FLD_GPIO_CORE_INTERRUPT_EN);
826827
} else if (irq_num == IRQ_GPIO2_RISC1) {
827-
BM_SET(GPIO_IRQ_REG, FLD_GPIO_IRQ_LVL_GPIO2RISC1);
828+
BM_SET(GPIO_IRQ_REG, FLD_GPIO_CORE_INTERRUPT_EN);
828829
}
829830

830831
riscv_plic_irq_enable(IRQ_TO_L2(irq_num));
831832
riscv_plic_set_priority(IRQ_TO_L2(irq_num), irq_priority);
832833

833834
if (irq_num == IRQ_GPIO) {
834-
BM_CLR(GPIO_IRQ_REG, FLD_GPIO_IRQ_LVL_GPIO);
835+
BM_CLR(GPIO_IRQ_REG, FLD_GPIO_CORE_INTERRUPT_EN);
835836
} else if (irq_num == IRQ_GPIO2_RISC0) {
836-
BM_CLR(GPIO_IRQ_REG, FLD_GPIO_IRQ_LVL_GPIO2RISC0);
837+
BM_CLR(GPIO_IRQ_REG, FLD_GPIO_CORE_INTERRUPT_EN);
837838
} else if (irq_num == IRQ_GPIO2_RISC1) {
838-
BM_CLR(GPIO_IRQ_REG, FLD_GPIO_IRQ_LVL_GPIO2RISC1);
839+
BM_CLR(GPIO_IRQ_REG, FLD_GPIO_CORE_INTERRUPT_EN);
839840
}
840841
}
841842
}
@@ -855,7 +856,7 @@ static int gpio_tlx_pm_action(const struct device *dev, enum pm_device_action ac
855856
data->gpio_tlx_retention.analog_in_conf
856857
= analog_read_reg8(areg_gpio_pc_ie);
857858
#if CONFIG_SOC_RISCV_TELINK_TL321X
858-
} else if (IS_PORT_B(gpio) && ((pin >= 4) && (pin <= 7))) {
859+
} else if (IS_PORT_B(gpio)) {
859860
data->gpio_tlx_retention.analog_in_conf
860861
= analog_read_reg8(areg_gpio_pb_ie);
861862
#elif CONFIG_SOC_RISCV_TELINK_TL721X

‎dts/bindings/power/telink,tl321x-power.yaml

+1
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@ properties:
1616
required: true
1717
enum:
1818
- "LDO_1P25_LDO_1P8"
19+
- "DCDC_1P25_LDO_1P8"
1920

2021
vbat-type:
2122
type: string

‎dts/riscv/telink/telink_tl321x.dtsi

+3-3
Original file line numberDiff line numberDiff line change
@@ -38,8 +38,8 @@
3838
state0: state0 {
3939
compatible = "zephyr,power-state";
4040
power-state-name = "suspend-to-idle";
41-
min-residency-us = <500>;
42-
exit-latency-us = <10>;
41+
min-residency-us = <20000>;
42+
exit-latency-us = <3000>;
4343
};
4444
};
4545

@@ -81,7 +81,7 @@
8181
power: power@80140180 {
8282
compatible = "telink,tl321x-power";
8383
reg = <0x80140180 0x40>;
84-
power-mode = "LDO_1P25_LDO_1P8";
84+
power-mode = "DCDC_1P25_LDO_1P8";
8585
vbat-type = "VBAT_MAX_VALUE_GREATER_THAN_3V6";
8686
status = "okay";
8787
};

‎soc/telink/tlsr/telink_tlx/linker.ld

+1-1
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ MEMORY
3232
RAM_ILM_N (rwx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(ram_ilm_nonretention)), LENGTH = DT_REG_SIZE(DT_NODELABEL(ram_ilm_nonretention))
3333
RAM_DLM (rwx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(ram_dlm)), LENGTH = DT_REG_SIZE(DT_NODELABEL(ram_dlm))
3434
#elif CONFIG_SOC_RISCV_TELINK_TL321X
35-
35+
RAM_ILM_N (rwx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(ram_ilm_nonretention)), LENGTH = DT_REG_SIZE(DT_NODELABEL(ram_ilm_nonretention))
3636
#endif
3737
#endif /* CONFIG_SOC_SERIES_RISCV_TELINK_TLX_RETENTION */
3838
}

‎soc/telink/tlsr/telink_tlx/telink_tlx_regions.ld

+12-3
Original file line numberDiff line numberDiff line change
@@ -31,9 +31,18 @@
3131
#define TELINK_RAM_CODE_REGION RAMABLE_REGION
3232
#endif
3333
#elif CONFIG_SOC_RISCV_TELINK_TL321X
34-
#define TELINK_RAM_DATA_REGION RAMABLE_REGION
35-
#define TELINK_RAM_CODE_BLE_REGION RAMABLE_REGION
36-
#define TELINK_RAM_CODE_REGION RAMABLE_REGION
34+
#if CONFIG_PM
35+
#define TELINK_RAM_DATA_REGION RAM_ILM_N
36+
#define TELINK_RAM_CODE_BLE_REGION RAM_ILM_N
37+
#else
38+
#define TELINK_RAM_DATA_REGION RAMABLE_REGION
39+
#define TELINK_RAM_CODE_BLE_REGION RAMABLE_REGION
40+
#endif
41+
#if CONFIG_SOC_SERIES_RISCV_TELINK_TLX_NON_RETENTION_RAM_CODE
42+
#define TELINK_RAM_CODE_REGION RAM_ILM_N
43+
#else
44+
#define TELINK_RAM_CODE_REGION RAMABLE_REGION
45+
#endif
3746
#endif
3847

3948
#endif /* CONFIG_SOC_SERIES_RISCV_TELINK_TLX_RETENTION */

‎west.yml

+1-1
Original file line numberDiff line numberDiff line change
@@ -239,7 +239,7 @@ manifest:
239239
- hal
240240
- name: hal_telink
241241
url: https://github.com/telink-semi/hal_telink
242-
revision: 74a83a3246ec83570000e75ad9d30bc6bbb7a322
242+
revision: d45ad1d5772528d8e3efc23fdcf8478cab7956f9
243243
path: modules/hal/telink
244244
groups:
245245
- hal

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