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gbernatxintelaescolar
gbernatxintel
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soc: intel: renamed soc from ace30_ptl to ace30
Renamed soc from ace30_ptl to ace30. We were previously using the wrong soc name. The correct name is ace30. There is only one ptl platform, but there can be several ace30 platforms. Signed-off-by: Grzegorz Bernat <grzegorzx.bernat@intel.com>
1 parent 966abb2 commit a654bfb

29 files changed

+740
-44
lines changed

‎boards/intel/adsp/Kconfig.intel_adsp

+2-2
Original file line numberDiff line numberDiff line change
@@ -8,5 +8,5 @@ config BOARD_INTEL_ADSP
88
select SOC_INTEL_ACE15_MTPM if BOARD_INTEL_ADSP_ACE15_MTPM_SIM
99
select SOC_INTEL_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL
1010
select SOC_INTEL_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL_SIM
11-
select SOC_INTEL_ACE30_PTL if BOARD_INTEL_ADSP_ACE30_PTL
12-
select SOC_INTEL_ACE30_PTL if BOARD_INTEL_ADSP_ACE30_PTL_SIM
11+
select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL
12+
select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL_SIM

‎boards/intel/adsp/board.yml

+4-2
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,8 @@ boards:
1111
- name: ace20_lnl
1212
variants:
1313
- name: 'sim'
14-
- name: ace30_ptl
14+
- name: ace30
1515
variants:
16-
- name: 'sim'
16+
- name: 'ptl'
17+
variants:
18+
- name: 'sim'

‎boards/intel/adsp/intel_adsp_ace30_defconfig

+12
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
# SPDX-License-Identifier: Apache-2.0
2+
3+
CONFIG_MAIN_STACK_SIZE=4096
4+
5+
CONFIG_GEN_ISR_TABLES=y
6+
CONFIG_GEN_IRQ_VECTOR_TABLE=n
7+
8+
CONFIG_BUILD_OUTPUT_BIN=n
9+
10+
CONFIG_DAI_SSP_HAS_POWER_CONTROL=y
11+
12+
CONFIG_DCACHE_LINE_SIZE=64

‎boards/intel/adsp/intel_adsp_ace30_ptl.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
identifier: intel_adsp/ace30_ptl
1+
identifier: intel_adsp/ace30/ptl
22
name: ACE 3.0 Panther Lake Audio DSP
33
type: mcu
44
arch: xtensa

‎boards/intel/adsp/intel_adsp_ace30_ptl_sim.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
identifier: intel_adsp/ace30_ptl/sim
1+
identifier: intel_adsp/ace30/ptl/sim
22
name: ACE 3.0 Panther Lake Audio DSP
33
type: sim
44
simulation: custom

‎drivers/dai/intel/dmic/dmic.c

+7-7
Original file line numberDiff line numberDiff line change
@@ -160,7 +160,7 @@ static inline void dai_dmic_release_ownership(const struct dai_intel_dmic *dmic)
160160

161161
static inline uint32_t dai_dmic_base(const struct dai_intel_dmic *dmic)
162162
{
163-
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
163+
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30)
164164
return dmic->hdamldmic_base;
165165
#else
166166
return dmic->shim_base;
@@ -173,7 +173,7 @@ static inline void dai_dmic_set_sync_period(uint32_t period, const struct dai_in
173173
uint32_t val = CONFIG_DAI_DMIC_HW_IOCLK / period - 1;
174174
uint32_t base = dai_dmic_base(dmic);
175175
/* DMIC Change sync period */
176-
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
176+
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30)
177177
sys_write32(sys_read32(base + DMICSYNC_OFFSET) | FIELD_PREP(DMICSYNC_SYNCPRD, val),
178178
base + DMICSYNC_OFFSET);
179179
sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_SYNCPU,
@@ -287,7 +287,7 @@ static void dai_dmic_irq_handler(const void *data)
287287
static inline void dai_dmic_dis_clk_gating(const struct dai_intel_dmic *dmic)
288288
{
289289
/* Disable DMIC clock gating */
290-
#if (CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL)
290+
#if (CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30)
291291
sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) | DMICLVSCTL_DCGD),
292292
dmic->vshim_base + DMICLVSCTL_OFFSET);
293293
#else
@@ -299,7 +299,7 @@ static inline void dai_dmic_dis_clk_gating(const struct dai_intel_dmic *dmic)
299299
static inline void dai_dmic_en_clk_gating(const struct dai_intel_dmic *dmic)
300300
{
301301
/* Enable DMIC clock gating */
302-
#if (CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL)
302+
#if (CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30)
303303
sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) & ~DMICLVSCTL_DCGD),
304304
dmic->vshim_base + DMICLVSCTL_OFFSET);
305305
#else /* All other CAVS and ACE platforms */
@@ -313,7 +313,7 @@ static inline void dai_dmic_program_channel_map(const struct dai_intel_dmic *dmi
313313
const struct dai_config *cfg,
314314
uint32_t index)
315315
{
316-
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
316+
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30)
317317
uint16_t pcmsycm = cfg->link_config;
318318
uint32_t reg_add = dmic->shim_base + DMICXPCMSyCM_OFFSET + 0x0004*index;
319319

@@ -322,7 +322,7 @@ static inline void dai_dmic_program_channel_map(const struct dai_intel_dmic *dmi
322322
ARG_UNUSED(dmic);
323323
ARG_UNUSED(cfg);
324324
ARG_UNUSED(index);
325-
#endif /* defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) */
325+
#endif /* defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) */
326326
}
327327

328328
static inline void dai_dmic_en_power(const struct dai_intel_dmic *dmic)
@@ -332,7 +332,7 @@ static inline void dai_dmic_en_power(const struct dai_intel_dmic *dmic)
332332
sys_write32((sys_read32(base + DMICLCTL_OFFSET) | DMICLCTL_SPA),
333333
base + DMICLCTL_OFFSET);
334334

335-
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
335+
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30)
336336
while (!(sys_read32(base + DMICLCTL_OFFSET) & DMICLCTL_CPA)) {
337337
k_sleep(K_USEC(100));
338338
}

‎drivers/dai/intel/dmic/dmic.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -173,7 +173,7 @@ struct dai_intel_dmic {
173173
/* hardware parameters */
174174
uint32_t reg_base;
175175
uint32_t shim_base;
176-
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
176+
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30)
177177
uint32_t hdamldmic_base;
178178
uint32_t vshim_base;
179179
#endif

‎drivers/dai/intel/dmic/dmic_nhlt.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -282,7 +282,7 @@ static int dai_nhlt_dmic_dai_params_get(struct dai_intel_dmic *dmic, const int c
282282
static inline void dai_dmic_clock_select_set(const struct dai_intel_dmic *dmic, uint32_t source)
283283
{
284284
uint32_t val;
285-
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) /* ACE 2.0,3.0 */
285+
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) /* ACE 2.0,3.0 */
286286
val = sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET);
287287
val &= ~DMICLVSCTL_MLCS;
288288
val |= FIELD_PREP(DMICLVSCTL_MLCS, source);
@@ -303,7 +303,7 @@ static inline void dai_dmic_clock_select_set(const struct dai_intel_dmic *dmic,
303303
static inline uint32_t dai_dmic_clock_select_get(const struct dai_intel_dmic *dmic)
304304
{
305305
uint32_t val;
306-
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) /* ACE 2.0,3.0 */
306+
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) /* ACE 2.0,3.0 */
307307
val = sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET);
308308
return FIELD_GET(DMICLVSCTL_MLCS, val);
309309
#else

‎drivers/dai/intel/ssp/dai-params-intel-ipc4.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -269,7 +269,7 @@ struct dai_intel_ipc4_ssp_mclk_config_2 {
269269
} __packed;
270270

271271
struct dai_intel_ipc4_ssp_driver_config {
272-
#ifdef CONFIG_SOC_INTEL_ACE30_PTL
272+
#ifdef CONFIG_SOC_INTEL_ACE30
273273
struct dai_intel_ipc4_ssp_config_ver_3_0 i2s_config;
274274
#else
275275
struct dai_intel_ipc4_ssp_config i2s_config;

‎drivers/dai/intel/ssp/ssp.c

+15-15
Original file line numberDiff line numberDiff line change
@@ -800,7 +800,7 @@ static void dai_ssp_pm_runtime_en_ssp_power(struct dai_intel_ssp *dp, uint32_t s
800800
ret = dai_ssp_poll_for_register_delay(dai_ip_base(dp) + I2SLCTL_OFFSET,
801801
I2SLCTL_CPA(ssp_index), I2SLCTL_CPA(ssp_index),
802802
DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE);
803-
#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL
803+
#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30
804804
sys_write32(sys_read32(dai_hdamlssp_base(dp) + I2SLCTL_OFFSET) |
805805
I2SLCTL_SPA(ssp_index),
806806
dai_hdamlssp_base(dp) + I2SLCTL_OFFSET);
@@ -835,7 +835,7 @@ static void dai_ssp_pm_runtime_dis_ssp_power(struct dai_intel_ssp *dp, uint32_t
835835
I2SLCTL_CPA(ssp_index), 0,
836836
DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE);
837837

838-
#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL
838+
#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30
839839
sys_write32(sys_read32(dai_hdamlssp_base(dp) + I2SLCTL_OFFSET) & (~I2SLCTL_SPA(ssp_index)),
840840
dai_hdamlssp_base(dp) + I2SLCTL_OFFSET);
841841

@@ -873,7 +873,7 @@ static void dai_ssp_program_channel_map(struct dai_intel_ssp *dp,
873873
/* Program HDA input stream parameters */
874874
sys_write16((pcmsycm & 0xffff), reg_add);
875875
}
876-
#elif defined(CONFIG_SOC_INTEL_ACE30_PTL)
876+
#elif defined(CONFIG_SOC_INTEL_ACE30)
877877
const struct dai_intel_ipc4_ssp_configuration_blob_ver_3_0 *blob30 = spec_config;
878878
const struct dai_intel_ipc4_ssp_configuration_blob *blob = spec_config;
879879
uint64_t time_slot_map = 0;
@@ -930,7 +930,7 @@ static void dai_ssp_empty_tx_fifo(struct dai_intel_ssp *dp)
930930
* SSSR_TNF is cleared when TX FIFO is empty or full,
931931
* so wait for set TNF then for TFL zero - order matter.
932932
*/
933-
#ifdef CONFIG_SOC_INTEL_ACE30_PTL
933+
#ifdef CONFIG_SOC_INTEL_ACE30
934934
ret = dai_ssp_poll_for_register_delay(dai_base(dp) + SSMODyCS(dp->tdm_slot_group),
935935
SSMODyCS_TNF, SSMODyCS_TNF,
936936
DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE);
@@ -959,7 +959,7 @@ static void dai_ssp_empty_tx_fifo(struct dai_intel_ssp *dp)
959959
}
960960
}
961961

962-
#ifdef CONFIG_SOC_INTEL_ACE30_PTL
962+
#ifdef CONFIG_SOC_INTEL_ACE30
963963
static void ssp_empty_rx_fifo_on_start(struct dai_intel_ssp *dp)
964964
{
965965
uint32_t retry = DAI_INTEL_SSP_RX_FLUSH_RETRY_MAX;
@@ -1191,7 +1191,7 @@ static int dai_ssp_bclk_prepare_enable(struct dai_intel_ssp *dp)
11911191
mdiv = ft[DAI_INTEL_SSP_DEFAULT_IDX].freq / ssp_plat_data->params.bclk_rate;
11921192
#endif
11931193

1194-
#ifndef CONFIG_SOC_INTEL_ACE30_PTL
1194+
#ifndef CONFIG_SOC_INTEL_ACE30
11951195
if (need_ecs) {
11961196
sscr0 |= SSCR0_ECS;
11971197
}
@@ -1724,7 +1724,7 @@ static int dai_ssp_set_config_tplg(struct dai_intel_ssp *dp, const struct dai_co
17241724
sys_write32(sspsp2, dai_base(dp) + SSPSP2);
17251725
sys_write32(ssioc, dai_base(dp) + SSIOC);
17261726
sys_write32(ssto, dai_base(dp) + SSTO);
1727-
#ifdef CONFIG_SOC_INTEL_ACE30_PTL
1727+
#ifdef CONFIG_SOC_INTEL_ACE30
17281728
for (uint32_t idx = 0; idx < I2SIPCMC; ++idx) {
17291729
sys_write64(sstsa, dai_base(dp) + SSMODyTSA(idx));
17301730
}
@@ -1777,7 +1777,7 @@ static int dai_ssp_set_config_tplg(struct dai_intel_ssp *dp, const struct dai_co
17771777
ssp_plat_data->clk_active |= SSP_CLK_BCLK_ES_REQ;
17781778

17791779
if (enable_sse) {
1780-
#ifdef CONFIG_SOC_INTEL_ACE30_PTL
1780+
#ifdef CONFIG_SOC_INTEL_ACE30
17811781
dai_ssp_update_bits(dp, SSMIDyCS(dp->tdm_slot_group),
17821782
SSMIDyCS_RSRE, SSMIDyCS_RSRE);
17831783
dai_ssp_update_bits(dp, SSMODyCS(dp->tdm_slot_group),
@@ -1806,7 +1806,7 @@ static int dai_ssp_set_config_tplg(struct dai_intel_ssp *dp, const struct dai_co
18061806
LOG_INF("hw_free stage: releasing BCLK clocks for SSP%d...",
18071807
dp->dai_index);
18081808
if (ssp_plat_data->clk_active & SSP_CLK_BCLK_ACTIVE) {
1809-
#ifdef CONFIG_SOC_INTEL_ACE30_PTL
1809+
#ifdef CONFIG_SOC_INTEL_ACE30
18101810
for (uint32_t idx = 0; idx < I2SOPCMC; ++idx) {
18111811
dai_ssp_update_bits(dp, SSMODyCS(idx), SSMODyCS_TSRE, 0);
18121812
}
@@ -1985,7 +1985,7 @@ static int dai_ssp_parse_tlv(struct dai_intel_ssp *dp, const uint8_t *aux_ptr, s
19851985
~I2CLCTL_MLCS(0x7)) |
19861986
I2CLCTL_MLCS(link->clock_source), dai_ip_base(dp) +
19871987
I2SLCTL_OFFSET);
1988-
#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL
1988+
#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30
19891989
sys_write32((sys_read32(dai_i2svss_base(dp) + I2SLCTL_OFFSET) &
19901990
~I2CLCTL_MLCS(0x7)) |
19911991
I2CLCTL_MLCS(link->clock_source),
@@ -2065,7 +2065,7 @@ static int dai_ssp_set_clock_control_ver_1(struct dai_intel_ssp *dp,
20652065
return 0;
20662066
}
20672067

2068-
#ifdef CONFIG_SOC_INTEL_ACE30_PTL
2068+
#ifdef CONFIG_SOC_INTEL_ACE30
20692069
static void dai_ssp_set_reg_config(struct dai_intel_ssp *dp, const struct dai_config *cfg,
20702070
const void *spec_config)
20712071
{
@@ -2184,7 +2184,7 @@ static int dai_ssp_set_config_blob(struct dai_intel_ssp *dp, const struct dai_co
21842184
struct dai_intel_ssp_plat_data *ssp_plat_data = dai_get_plat_data(dp);
21852185
int err;
21862186

2187-
#ifdef CONFIG_SOC_INTEL_ACE30_PTL
2187+
#ifdef CONFIG_SOC_INTEL_ACE30
21882188
dp->tdm_slot_group = cfg->tdm_slot_group;
21892189
#endif
21902190

@@ -2322,7 +2322,7 @@ static void dai_ssp_start(struct dai_intel_ssp *dp, int direction)
23222322

23232323

23242324
/* enable DMA */
2325-
#if CONFIG_SOC_INTEL_ACE30_PTL
2325+
#if CONFIG_SOC_INTEL_ACE30
23262326
if (direction == DAI_DIR_PLAYBACK) {
23272327
dai_ssp_update_bits(dp, SSMODyCS(dp->tdm_slot_group),
23282328
SSMODyCS_TSRE, SSMODyCS_TSRE);
@@ -2392,7 +2392,7 @@ static void dai_ssp_stop(struct dai_intel_ssp *dp, int direction)
23922392
if (direction == DAI_DIR_CAPTURE &&
23932393
dp->state[DAI_DIR_CAPTURE] != DAI_STATE_PRE_RUNNING) {
23942394
LOG_INF("SSP%d RX", dp->dai_index);
2395-
#if CONFIG_SOC_INTEL_ACE30_PTL
2395+
#if CONFIG_SOC_INTEL_ACE30
23962396
dai_ssp_update_bits(dp, SSMIDyCS(dp->tdm_slot_group), SSMIDyCS_RXEN, 0);
23972397
dai_ssp_update_bits(dp, SSMIDyCS(dp->tdm_slot_group), SSMIDyCS_RSRE, 0);
23982398
#else
@@ -2407,7 +2407,7 @@ static void dai_ssp_stop(struct dai_intel_ssp *dp, int direction)
24072407
if (direction == DAI_DIR_PLAYBACK &&
24082408
dp->state[DAI_DIR_PLAYBACK] != DAI_STATE_PRE_RUNNING) {
24092409
LOG_INF("SSP%d TX", dp->dai_index);
2410-
#if CONFIG_SOC_INTEL_ACE30_PTL
2410+
#if CONFIG_SOC_INTEL_ACE30
24112411
dai_ssp_update_bits(dp, SSMODyCS(dp->tdm_slot_group), SSMODyCS_TSRE, 0);
24122412
dai_ssp_empty_tx_fifo(dp);
24132413
dai_ssp_update_bits(dp, SSMODyCS(dp->tdm_slot_group), SSMODyCS_TXEN, 0);

‎drivers/dai/intel/ssp/ssp.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,7 @@
5252
#include "ssp_regs_v1.h"
5353
#elif defined(CONFIG_SOC_INTEL_ACE20_LNL)
5454
#include "ssp_regs_v2.h"
55-
#elif defined(CONFIG_SOC_INTEL_ACE30_PTL)
55+
#elif defined(CONFIG_SOC_INTEL_ACE30)
5656
#include "ssp_regs_v3.h"
5757
#else
5858
#error "Missing ssp definitions"
@@ -116,7 +116,7 @@ struct dai_intel_ssp_plat_data {
116116
uint32_t base;
117117
uint32_t ip_base;
118118
uint32_t shim_base;
119-
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
119+
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30)
120120
uint32_t hdamlssp_base;
121121
uint32_t i2svss_base;
122122
#endif

‎drivers/dma/dma_intel_adsp_hda.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -235,7 +235,7 @@ int intel_adsp_hda_dma_status(const struct device *dev, uint32_t channel,
235235
stat->pending_length = used;
236236
stat->free = unused;
237237

238-
#if CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL
238+
#if CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30
239239
/* Linear Link Position via HDA-DMA is only supported on ACE2 or newer */
240240
if (cfg->direction == MEMORY_TO_PERIPHERAL || cfg->direction == PERIPHERAL_TO_MEMORY) {
241241
uint32_t tmp;

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