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simple_reorder.hpp
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/*******************************************************************************
* Copyright 2016-2025 Intel Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#ifndef CPU_REORDER_SIMPLE_REORDER_HPP
#define CPU_REORDER_SIMPLE_REORDER_HPP
#include <algorithm>
#include <assert.h>
#include "common/bfloat16.hpp"
#include "common/c_types_map.hpp"
#include "common/dnnl_thread.hpp"
#include "common/math_utils.hpp"
#include "common/primitive.hpp"
#include "common/primitive_attr.hpp"
#include "common/tag_traits.hpp"
#include "common/type_helpers.hpp"
#include "common/utils.hpp"
#include "cpu/cpu_primitive.hpp"
#include "cpu/reorder/cpu_reorder_pd.hpp"
#include "cpu/simple_q10n.hpp"
namespace dnnl {
namespace impl {
namespace cpu {
using bd = block_dim_t;
using ib = inner_blk_t;
template <impl::data_type_t type>
using data_t = typename prec_traits_t<type>::type;
template <impl::data_type_t type_i, impl::data_type_t type_o>
using _qz_a1b0 = q10n::qz_a1b0_t<data_t<type_i>, data_t<type_o>>;
template <impl::data_type_t type_i, impl::data_type_t type_o>
using _qz = q10n::qz_t<data_t<type_i>, data_t<type_o>>;
namespace fmt_order {
const bool keep = true;
const bool reverse = false;
const bool any = keep;
} // namespace fmt_order
namespace spec {
struct direct_copy {};
struct direct_copy_except_dim_0 {};
struct reference {};
struct conv_req_comp {}; // {s8, u8: asymmetric quantization}
} // namespace spec
#define SIMPLE_REORDER_TEMPL_DECL \
impl::data_type_t type_i, impl::format_tag_t tag_i, \
impl::data_type_t type_o, impl::format_tag_t tag_o, \
bool order_keep
#define SIMPLE_REORDER_TEMPL_CALL type_i, tag_i, type_o, tag_o, order_keep
#define DECLARE_COMMON_PARAMS() \
auto input = CTX_IN_MEM(const data_t<type_i> *, DNNL_ARG_FROM); \
auto output = CTX_OUT_MEM(data_t<type_o> *, DNNL_ARG_TO); \
const auto &scratchpad = ctx.get_scratchpad_grantor(); \
MAYBE_UNUSED(scratchpad); \
const auto input_d = ctx.memory_mdw(DNNL_ARG_FROM, pd->src_md()); \
const auto output_d = ctx.memory_mdw(DNNL_ARG_TO, pd->dst_md()); \
DEFINE_ARG_SCALES_BUFFER_ATTR(pd->attr(), src_scales, DNNL_ARG_FROM); \
DEFINE_ARG_SCALES_BUFFER_ATTR(pd->attr(), dst_scales_, DNNL_ARG_TO); \
const auto src_scales_d \
= ctx.memory_mdw(DNNL_ARG_ATTR_SCALES | DNNL_ARG_FROM); \
MAYBE_UNUSED(src_scales_d); \
int src_scales_mask, dst_scales_mask; \
CHECK(get_scales_mask(pd->attr(), &src_scales_mask, &dst_scales_mask)); \
int scales_mask = std::max(src_scales_mask, dst_scales_mask); \
MAYBE_UNUSED(scales_mask); \
dim_t D_start, D_mask, D_rest; \
pd->get_D_values(input_d, scales_mask, &D_start, &D_mask, &D_rest); \
const float *dst_scales = pd->precompute_scales( \
scratchpad, pd->attr(), D_mask, dst_scales_); \
MAYBE_UNUSED(dst_scales); \
DEFINE_ZERO_POINTS_BUFFER_ATTR(pd->attr(), src_zero_points, DNNL_ARG_FROM) \
const auto src_zps_d \
= ctx.memory_mdw(DNNL_ARG_ATTR_ZERO_POINTS | DNNL_ARG_FROM); \
MAYBE_UNUSED(src_zps_d); \
int src_zp = src_zero_points ? src_zero_points[0] : 0; \
MAYBE_UNUSED(src_zp); \
DEFINE_ZERO_POINT_VALUE_ATTR(pd->attr(), dst_zp, DNNL_ARG_TO); \
const float alpha = src_scales[0] * dst_scales[0]; \
MAYBE_UNUSED(alpha); \
const float beta = pd->beta(); \
MAYBE_UNUSED(beta);
#define GET_SCRATCHPAD_SIZE_ZERO() \
static size_t get_scratchpad_size(const memory_desc_wrapper &input_d, \
const memory_desc_wrapper &output_d) { \
return 0; \
}
/* specific reorders: common template */
template <SIMPLE_REORDER_TEMPL_DECL, typename spec = void>
struct simple_reorder_impl {};
namespace {
inline bool simple_fmt_check(bool order_keep, impl::format_tag_t tag_i,
impl::format_tag_t tag_o, const memory_desc_wrapper &input_d,
const memory_desc_wrapper &output_d) {
if (input_d.has_runtime_dims_or_strides()) return false;
return input_d.matches_tag(order_keep ? tag_i : tag_o)
&& output_d.matches_tag(order_keep ? tag_o : tag_i);
}
inline bool simple_po_check(const primitive_attr_t *attr) {
const auto &po = attr->post_ops_;
return po.len() == 0 || (po.len() == 1 && po.entry_[0].is_sum(false));
}
inline status_t get_scales_mask(
const primitive_attr_t *attr, int *src_mask, int *dst_mask) {
const auto &s = attr->scales_;
if (src_mask == nullptr || dst_mask == nullptr)
return status::invalid_arguments;
*src_mask = 0;
if (!s.has_default_values(DNNL_ARG_SRC))
*src_mask = s.get_mask(DNNL_ARG_SRC);
*dst_mask = 0;
if (!s.has_default_values(DNNL_ARG_DST))
*dst_mask = s.get_mask(DNNL_ARG_DST);
// This is used in a check function.
if (*src_mask > 0 && *dst_mask > 0 && *dst_mask != *src_mask)
return status::invalid_arguments;
return status::success;
}
inline bool simple_attr_check(const primitive_attr_t *attr,
bool many_scales_support, bool sum_support) {
using smask_t = primitive_attr_t::skip_mask_t;
smask_t skip_mask = smask_t::scales;
if (sum_support) skip_mask = skip_mask | smask_t::post_ops;
if (!attr->has_default_values(skip_mask)) return false;
for (int arg : {DNNL_ARG_SRC, DNNL_ARG_DST}) {
// Data type for scales is not generally supported.
if (!attr->scales_.has_default_data_type(arg)) return false;
// Groups are generally not supported.
if (!attr->scales_.get(arg).has_default_groups()) return false;
}
if (many_scales_support) return true;
int src_mask, dst_mask;
if (get_scales_mask(attr, &src_mask, &dst_mask) != status::success)
return false;
return src_mask == 0 && dst_mask == 0;
}
// TODO: once re-factor for quantization happens, for each entry maintain a md
// in complaince with correspondent argument for easier offset computation.
inline status_t get_quant_md(memory_desc_t &md, const int ndims,
const dims_t in_dims, const int quant_mask, const dim_t g0,
const dim_t g1, const data_type_t dt) {
dims_t quant_dims {};
// TODO: incorporate groups into `utils::copy_dims_with_mask` to simplify
// the logic.
utils::copy_dims_with_mask(quant_dims, in_dims, ndims, quant_mask,
/* fill_with_ones = */ true);
if (ndims >= 2) {
if (utils::one_of(0, g0, g1)) return status::runtime_error;
quant_dims[ndims - 1] /= g1;
quant_dims[ndims - 2] /= g0;
}
CHECK(memory_desc_init_by_tag(
md, ndims, quant_dims, dt, get_abx_tag(ndims)));
return status::success;
}
// Returns an offset of a quantization entry based on logical offset dimensions
// of the correspondent input - `input_idx`, `quant_mask`, groups `g0` and
// `g1` when they are supported (otherwise, pass `1`), and `quant_dims`.
//
// Offset is always concide with logical index because quantization entries
// don't have a notion of physical formats.
inline dim_t get_quant_off(const dims_t &input_idx, const int ndims,
const int quant_mask, const dim_t g0, const dim_t g1,
const memory_desc_t &quant_md) {
dims_t quant_idx {};
utils::array_copy(quant_idx, input_idx, ndims);
utils::apply_mask_on_dims(quant_idx, ndims, quant_mask);
// Note: an `idx` must divide by a group value as grouped quantization
// applies to consecutive points.
// Using quant dimensions in `l_dims_by_l_offset` will lead to wrapping
// around dimensions instead of applying consecutively.
if (ndims >= 2) {
quant_idx[ndims - 1] /= g1;
quant_idx[ndims - 2] /= g0;
}
const memory_desc_wrapper q_mdw(quant_md);
return q_mdw.off_v(quant_idx);
}
} // namespace
/* specific reorders: implementation */
template <SIMPLE_REORDER_TEMPL_DECL>
struct simple_reorder_impl<SIMPLE_REORDER_TEMPL_CALL,
typename utils::enable_if<tag_i == format_tag::any
&& utils::one_of(tag_o, format_tag::wio,
format_tag::wigo, format_tag::hwio,
format_tag::hwigo, format_tag::dhwio,
format_tag::dhwigo),
spec::conv_req_comp>::type> {
static status_t is_applicable(const memory_desc_wrapper &input_d,
const memory_desc_wrapper &output_d, const primitive_attr_t *attr) {
using namespace data_type;
using namespace utils;
VDISPATCH_REORDER_IC(!input_d.has_runtime_dims_or_strides(),
VERBOSE_RUNTIMEDIM_UNSUPPORTED);
int src_scales_mask, dst_scales_mask;
CHECK(get_scales_mask(attr, &src_scales_mask, &dst_scales_mask));
int scales_mask = std::max(src_scales_mask, dst_scales_mask);
static constexpr bool w_groups = one_of(
tag_o, format_tag::wigo, format_tag::hwigo, format_tag::dhwigo);
const bool req_comp = output_d.extra().flags
& memory_extra_flags::compensation_conv_s8s8;
const bool req_asymmetric_comp = output_d.extra().flags
& memory_extra_flags::compensation_conv_asymmetric_src;
auto mask_ok = [&](bool check, int mask) {
return IMPLICATION(check, mask == (w_groups ? 0x3 : 0x1));
};
VDISPATCH_REORDER_IC(one_of(input_d.data_type(), f32, s8, bf16),
VERBOSE_UNSUPPORTED_DT);
VDISPATCH_REORDER_IC(
output_d.data_type() == s8, VERBOSE_UNSUPPORTED_DT);
VDISPATCH_REORDER_IC(
simple_attr_check(attr, true, false), VERBOSE_UNSUPPORTED_ATTR);
VDISPATCH_REORDER_IC(
input_d.is_plain(), VERBOSE_UNSUPPORTED_TENSOR_LAYOUT, "src");
VDISPATCH_REORDER_IC(output_d.matches_tag(tag_o),
VERBOSE_UNSUPPORTED_TENSOR_LAYOUT, "dst");
VDISPATCH_REORDER_IC(
(req_comp || req_asymmetric_comp), "compensation is required");
VDISPATCH_REORDER_IC(
mask_ok(req_comp, output_d.extra().compensation_mask),
VERBOSE_UNSUPPORTED_FEATURE, "s8s8 compensation configuration");
VDISPATCH_REORDER_IC(mask_ok(req_asymmetric_comp,
output_d.extra().asymm_compensation_mask),
VERBOSE_UNSUPPORTED_FEATURE,
"zero-points compensation configuration");
VDISPATCH_REORDER_IC(
IMPLICATION(!w_groups, one_of(scales_mask, 0, 0x1)),
VERBOSE_UNSUPPORTED_SCALES_CFG);
VDISPATCH_REORDER_IC(IMPLICATION(w_groups, one_of(scales_mask, 0, 0x3)),
VERBOSE_UNSUPPORTED_SCALES_CFG);
return status::success;
}
GET_SCRATCHPAD_SIZE_ZERO();
static status_t execute(const cpu_reorder_pd_t *pd, const exec_ctx_t &ctx) {
DECLARE_COMMON_PARAMS();
static constexpr bool w_groups = utils::one_of(
tag_o, format_tag::wigo, format_tag::hwigo, format_tag::dhwigo);
static constexpr bool w_height
= !utils::one_of(tag_o, format_tag::wio, format_tag::wigo);
static constexpr bool w_depth
= utils::one_of(tag_o, format_tag::dhwio, format_tag::dhwigo);
const auto &dims = input_d.dims();
const dim_t G = w_groups ? dims[0] : 1;
const dim_t OC = dims[w_groups + 0];
const dim_t IC = dims[w_groups + 1];
const dim_t D = w_depth ? dims[w_groups + 2] : 1;
const dim_t H = w_height ? dims[w_groups + w_depth + 2] : 1;
const dim_t W = dims[w_groups + w_depth + w_height + 2];
const bool req_comp = output_d.extra().flags
& memory_extra_flags::compensation_conv_s8s8;
const bool has_asymmetric_comp = output_d.extra().flags
& memory_extra_flags::compensation_conv_asymmetric_src;
assert(req_comp || has_asymmetric_comp);
float adj_scale
= (output_d.extra().flags & memory_extra_flags::scale_adjust)
? output_d.extra().scale_adjust
: 1.f;
size_t offset = output_d.size() - output_d.additional_buffer_size();
size_t comp_size = output_d.additional_buffer_size(
memory_extra_flags::compensation_conv_s8s8);
size_t zp_offset = offset + (req_comp ? comp_size : 0);
int32_t *cp = req_comp ? reinterpret_cast<int32_t *>(output + offset)
: nullptr;
int32_t *zp = has_asymmetric_comp
? reinterpret_cast<int32_t *>(output + zp_offset)
: nullptr;
const bool per_oc = scales_mask & (1 << (w_groups + 0));
const bool per_ic = scales_mask & (1 << (w_groups + 1));
const size_t ic_stride = per_ic ? 1 : 0;
const size_t oc_stride = per_oc ? per_ic ? IC : 1 : 0;
parallel_nd(G, OC, [&](dim_t g, dim_t oc) {
if (req_comp) cp[g * OC + oc] = 0;
if (has_asymmetric_comp) zp[g * OC + oc] = 0;
for_(dim_t ic = 0; ic < IC; ic++)
for_(dim_t d = 0; d < D; d++)
for_(dim_t h = 0; h < H; h++)
for (dim_t w = 0; w < W; w++) {
auto i = w_depth
? input[input_d.blk_off<!w_groups>(g, oc, ic, d, h, w)]
: w_height
? input[input_d.blk_off<!w_groups>(g, oc, ic, h, w)]
: input[input_d.blk_off<!w_groups>(g, oc, ic, w)];
auto &o = w_depth ? output[output_d.blk_off<!w_groups>(
g, oc, ic, d, h, w)]
: w_height
? output[output_d.blk_off<!w_groups>(g, oc, ic, h, w)]
: output[output_d.blk_off<!w_groups>(g, oc, ic, w)];
const size_t os_off
= (g * OC + oc) * oc_stride + ic * ic_stride;
const float s = src_scales[src_scales_mask == 0 ? 0 : os_off];
const float d = dst_scales[dst_scales_mask == 0 ? 0 : os_off];
o = q10n::qz_b0_t<data_t<type_i>, data_t<type_o>>()(
i, s * adj_scale * d);
if (req_comp) cp[g * OC + oc] -= (int32_t)o;
if (has_asymmetric_comp) zp[g * OC + oc] -= (int32_t)o;
}
if (req_comp) cp[g * OC + oc] *= 128;
});
return status::success;
}
};
template <SIMPLE_REORDER_TEMPL_DECL>
struct simple_reorder_impl<SIMPLE_REORDER_TEMPL_CALL,
typename utils::enable_if<
(utils::one_of(tag_i, format_tag::iwo, format_tag::oiw,
format_tag::wio)
&& utils::one_of(tag_o, format_tag::OIw4i16o4i,
format_tag::OIw4i32o4i, format_tag::OIw4i64o4i,
format_tag::OIw2i8o4i, format_tag::OIw4o4i))
|| (utils::one_of(tag_i, format_tag::oi, format_tag::io)
&& utils::one_of(tag_o, format_tag::OI4i16o4i,
format_tag::OI4i32o4i,
format_tag::OI4i64o4i))
|| (utils::one_of(
tag_i, format_tag::goiw, format_tag::wigo)
&& utils::one_of(tag_o, format_tag::gOIw4i16o4i,
format_tag::gOIw2i8o4i,
format_tag::gOIw4o4i))
|| (utils::one_of(tag_i, format_tag::ihwo,
format_tag::hwio, format_tag::oihw)
&& utils::one_of(tag_o, format_tag::OIhw4i16o4i,
format_tag::OIhw4i32o4i,
format_tag::OIhw4i64o4i,
format_tag::OIhw2i8o4i,
format_tag::OIhw4o4i))
|| (utils::one_of(tag_i, format_tag::idhwo,
format_tag::dhwio, format_tag::oidhw)
&& utils::one_of(tag_o,
format_tag::OIdhw4i16o4i,
format_tag::OIdhw4i32o4i,
format_tag::OIdhw4i64o4i,
format_tag::OIdhw2i8o4i,
format_tag::OIdhw4o4i))
|| (utils::one_of(
tag_i, format_tag::goihw, format_tag::hwigo)
&& utils::one_of(tag_o, format_tag::gOIhw4o4i,
format_tag::gOIhw2i8o4i,
format_tag::gOIhw4i16o4i))
|| (utils::one_of(tag_i, format_tag::goidhw)
&& (utils::one_of(tag_o,
format_tag::gOIdhw4i16o4i,
format_tag::gOIdhw2i8o4i,
format_tag::gOIdhw4o4i))),
spec::conv_req_comp>::type> {
static status_t is_applicable(const memory_desc_wrapper &input_d,
const memory_desc_wrapper &output_d, const primitive_attr_t *attr) {
using namespace format_tag;
using namespace data_type;
using namespace utils;
VDISPATCH_REORDER_IC(!input_d.has_runtime_dims_or_strides(),
VERBOSE_RUNTIMEDIM_UNSUPPORTED);
int src_scales_mask, dst_scales_mask;
CHECK(get_scales_mask(attr, &src_scales_mask, &dst_scales_mask));
int scales_mask = std::max(src_scales_mask, dst_scales_mask);
static constexpr bool w_groups = !one_of(tag_o, OIw4i16o4i, OIw2i8o4i,
OIw4o4i, OIhw4i16o4i, OIhw2i8o4i, OIhw4o4i, OIdhw4i16o4i,
OIdhw2i8o4i, OIdhw4o4i, OI4i16o4i, OI4i32o4i, OI4i64o4i,
OIw4i32o4i, OIw4i64o4i, OIhw4i32o4i, OIhw4i64o4i, OIdhw4i32o4i,
OIdhw4i64o4i);
const bool req_comp = output_d.extra().flags
& memory_extra_flags::compensation_conv_s8s8;
const bool req_asymmetric_comp = output_d.extra().flags
& memory_extra_flags::compensation_conv_asymmetric_src;
auto mask_ok = [&](bool check, int mask) {
return IMPLICATION(check, mask == (w_groups ? 0x3 : 0x1));
};
VDISPATCH_REORDER_IC(one_of(input_d.data_type(), f32, s8, bf16),
VERBOSE_UNSUPPORTED_DT);
VDISPATCH_REORDER_IC(
output_d.data_type() == s8, VERBOSE_UNSUPPORTED_DT);
VDISPATCH_REORDER_IC(
simple_attr_check(attr, true, false), VERBOSE_UNSUPPORTED_ATTR);
VDISPATCH_REORDER_IC(input_d.matches_tag(tag_i),
VERBOSE_UNSUPPORTED_TENSOR_LAYOUT, "src");
VDISPATCH_REORDER_IC(output_d.matches_tag(tag_o),
VERBOSE_UNSUPPORTED_TENSOR_LAYOUT, "dst");
VDISPATCH_REORDER_IC(
(req_comp || req_asymmetric_comp), "compensation is required");
VDISPATCH_REORDER_IC(
mask_ok(req_comp, output_d.extra().compensation_mask),
"s8s8 compensation configuration is not supported");
VDISPATCH_REORDER_IC(mask_ok(req_asymmetric_comp,
output_d.extra().asymm_compensation_mask),
"zero-points compensation configuration is not supported");
VDISPATCH_REORDER_IC(
IMPLICATION(!w_groups, one_of(scales_mask, 0, 0x1)),
VERBOSE_UNSUPPORTED_SCALES_CFG);
VDISPATCH_REORDER_IC(IMPLICATION(w_groups, one_of(scales_mask, 0, 0x3)),
VERBOSE_UNSUPPORTED_SCALES_CFG);
return status::success;
}
GET_SCRATCHPAD_SIZE_ZERO();
static status_t execute(const cpu_reorder_pd_t *pd, const exec_ctx_t &ctx) {
DECLARE_COMMON_PARAMS();
using namespace format_tag;
static constexpr bool w_groups = !utils::one_of(tag_o, OIw4o4i,
OIw4i16o4i, OIhw4i16o4i, OIdhw4i16o4i, OIhw4o4i, OIw2i8o4i,
OIhw2i8o4i, OIdhw2i8o4i, OIdhw4o4i, OI4i16o4i, OI4i32o4i,
OI4i64o4i, OIw4i32o4i, OIw4i64o4i, OIhw4i32o4i, OIhw4i64o4i,
OIdhw4i32o4i, OIdhw4i64o4i);
constexpr int is_0d
= utils::one_of(tag_o, OI4i16o4i, OI4i32o4i, OI4i64o4i);
constexpr int is_1d
= utils::one_of(tag_o, gOIw4i16o4i, OIw4i16o4i, gOIw2i8o4i,
OIw2i8o4i, gOIw4o4i, OIw4o4i, OIw4i32o4i, OIw4i64o4i);
constexpr int is_3d = utils::one_of(tag_o, gOIdhw4i16o4i, OIdhw4i16o4i,
gOIdhw2i8o4i, OIdhw2i8o4i, gOIdhw4o4i, OIdhw4o4i, OIdhw4i32o4i,
OIdhw4i64o4i);
constexpr dim_t icblksize
= utils::one_of(
tag_traits_t<tag_o>::inner_blks, ib::_4a4b, ib::_4b4c)
? 4
: utils::one_of(tag_traits_t<tag_o>::inner_blks, ib::_2c8b4c,
ib::_2b8a4b)
? 8
: 16;
constexpr dim_t ocblksize
= tag_traits_t<tag_o>::inner_blks == ib::_4b32a4b ? 32
: tag_traits_t<tag_o>::inner_blks == ib::_4b64a4b ? 64
: icblksize;
const auto &plain_d = order_keep ? input_d : output_d;
const auto &dims = input_d.dims();
const int ndims = input_d.ndims();
const auto &pdims
= order_keep ? output_d.padded_dims() : input_d.padded_dims();
const dim_t G = w_groups ? dims[0] : 1;
const dim_t OC = dims[w_groups + 0];
const dim_t PADDED_OC = pdims[w_groups + 0];
const dim_t NB_OC = pdims[w_groups + 0] / ocblksize;
const dim_t IC = dims[w_groups + 1];
const dim_t NB_IC = pdims[w_groups + 1] / icblksize;
const dim_t D = is_3d ? dims[2 + w_groups] : 1;
const dim_t H = is_1d || is_0d ? 1 : dims[2 + w_groups + is_3d];
const dim_t W = is_0d ? 1 : dims[w_groups + is_3d + 3 - is_1d];
// XXX: Currently user can pass a mask that has non-zero values in
// dimensions that do not exist in a md. Since attributes are created
// separately mask can't be validated.
// This line truncates a given mask in range [0, 1 << ndims - 1]
// TODO: Such masks can be either prohibited at pd creation step at
// API level or checked by each implementation that relies on it.
scales_mask &= (1 << ndims) - 1;
const bool req_comp = output_d.extra().flags
& memory_extra_flags::compensation_conv_s8s8;
const bool has_asymmetric_comp = output_d.extra().flags
& memory_extra_flags::compensation_conv_asymmetric_src;
assert(req_comp || has_asymmetric_comp);
float adj_scale
= (output_d.extra().flags & memory_extra_flags::scale_adjust)
? output_d.extra().scale_adjust
: 1.f;
const bool per_oc = scales_mask & (1 << (w_groups + 0));
const bool per_ic = scales_mask & (1 << (w_groups + 1));
const size_t ic_stride = per_ic ? 1 : 0;
const size_t oc_stride = per_oc ? per_ic ? IC : 1 : 0;
const size_t nb_ic_stride = (per_ic ? 1 : 0) * icblksize;
const size_t nb_oc_stride = (per_oc ? per_ic ? IC : 1 : 0) * ocblksize;
// This kernel is used primarily for tensors with multiple inner
// blocks for which generic zero padding must be used.
// TODO: apply zero padding inside parallel_nd()
ctx.zero_pad_output(DNNL_ARG_TO);
auto ker = [&](const data_t<type_i> *inp, data_t<type_o> *out,
int32_t *c, int32_t *zp, const float *s,
const float *d, const dim_t oc_block,
const dim_t ic_block) {
#define index AB_or_BC_blk_off<tag_traits_t<tag_o>::inner_blks>
for_(dim_t ic = 0; ic < ic_block; ++ic)
for (dim_t oc = 0; oc < oc_block; ++oc) {
const auto plain_off
= oc * plain_d.blocking_desc().strides[w_groups + 0]
+ ic * plain_d.blocking_desc().strides[w_groups + 1];
const size_t os_off = oc * oc_stride + ic * ic_stride;
const float src_scale = s[src_scales_mask == 0 ? 0 : os_off];
const float dst_scale = d[dst_scales_mask == 0 ? 0 : os_off];
out[index(oc, ic)]
= q10n::qz_b0_t<data_t<type_i>, data_t<type_o>>()(
inp[plain_off],
src_scale * adj_scale * dst_scale);
if (req_comp) c[oc] -= (128 * (int32_t)(out[index(oc, ic)]));
if (has_asymmetric_comp)
zp[oc] -= (int32_t)(out[index(oc, ic)]);
}
#undef index
};
constexpr dim_t i_mult_ic = icblksize;
constexpr dim_t i_mult_oc = ocblksize;
constexpr dim_t o_mult = 1;
size_t offset = output_d.size() - output_d.additional_buffer_size();
size_t comp_size = output_d.additional_buffer_size(
memory_extra_flags::compensation_conv_s8s8);
size_t zp_offset = offset + (req_comp ? comp_size : 0);
int32_t *cp = req_comp ? reinterpret_cast<int32_t *>(output + offset)
: nullptr;
int32_t *zp = has_asymmetric_comp
? reinterpret_cast<int32_t *>(output + zp_offset)
: nullptr;
parallel_nd(G * PADDED_OC, [&](dim_t i) {
if (req_comp) cp[i] = 0;
if (has_asymmetric_comp) zp[i] = 0;
});
#define wei_blk_off(md, g, o, i, d, h, w) \
(is_0d ? (md).blk_off<!w_groups>(g, o, i) \
: is_1d ? (md).blk_off<!w_groups>(g, o, i, w) \
: is_3d ? (md).blk_off<!w_groups>(g, o, i, d, h, w) \
: (md).blk_off<!w_groups>(g, o, i, h, w))
parallel_nd(G, NB_OC, [&](dim_t g, dim_t O) {
for_(dim_t I = 0; I < NB_IC; I++)
for_(dim_t d = 0; d < D; d++)
for_(dim_t h = 0; h < H; h++)
for (dim_t w = 0; w < W; w++) {
auto i = &input[wei_blk_off(
input_d, g, i_mult_oc * O, i_mult_ic * I, d, h, w)];
auto o = &output[wei_blk_off(
output_d, g, o_mult * O, o_mult * I, d, h, w)];
const dim_t oc_block = nstl::min(ocblksize, OC - O * ocblksize);
const dim_t ic_block = nstl::min(icblksize, IC - I * icblksize);
dim_t _offset = (g * NB_OC + O) * ocblksize;
dim_t os_nb_off
= (g * NB_OC + O) * nb_oc_stride + I * nb_ic_stride;
const float *src_scales_ptr
= &src_scales[src_scales_mask == 0 ? 0 : os_nb_off];
const float *dst_scales_ptr
= &dst_scales[dst_scales_mask == 0 ? 0 : os_nb_off];
ker(i, o, (order_keep && req_comp) ? &cp[_offset] : nullptr,
(order_keep && has_asymmetric_comp) ? &zp[_offset]
: nullptr,
src_scales_ptr, dst_scales_ptr, oc_block, ic_block);
}
});
#undef wei_blk_off
return status::success;
}
};
/* Asymmetric Blocking */
template <SIMPLE_REORDER_TEMPL_DECL>
struct simple_reorder_impl<SIMPLE_REORDER_TEMPL_CALL,
typename utils::enable_if<(utils::one_of(tag_i, format_tag::iwo,
format_tag::oiw, format_tag::wio)
&& utils::one_of(
tag_o, format_tag::Owi16o))
|| (utils::one_of(
tag_i, format_tag::goiw, format_tag::wigo)
&& utils::one_of(tag_o, format_tag::gOwi16o))
|| (utils::one_of(tag_i, format_tag::ihwo,
format_tag::hwio, format_tag::oihw)
&& utils::one_of(tag_o, format_tag::Owhi16o))
|| (utils::one_of(
tag_i, format_tag::goihw, format_tag::hwigo)
&& utils::one_of(tag_o, format_tag::gOwhi16o)),
spec::conv_req_comp>::type> {
static status_t is_applicable(const memory_desc_wrapper &input_d,
const memory_desc_wrapper &output_d, const primitive_attr_t *attr) {
using namespace format_tag;
using namespace data_type;
using namespace utils;
VDISPATCH_REORDER_IC(!input_d.has_runtime_dims_or_strides(),
VERBOSE_RUNTIMEDIM_UNSUPPORTED);
static constexpr bool w_groups = !one_of(tag_o, Owi16o, Owhi16o);
// Current formats are only used in jit kernels that natively
// support s8 instructions, hence, there is no need for signed
// compensation.
const bool req_comp = output_d.extra().flags
& memory_extra_flags::compensation_conv_s8s8;
const bool req_asymmetric_comp = output_d.extra().flags
& memory_extra_flags::compensation_conv_asymmetric_src;
auto mask_ok = [&](bool check, int mask) {
return IMPLICATION(check, mask == (w_groups ? 0x3 : 0x1));
};
VDISPATCH_REORDER_IC(one_of(input_d.data_type(), f32, s8, bf16),
VERBOSE_UNSUPPORTED_DT);
VDISPATCH_REORDER_IC(
output_d.data_type() == s8, VERBOSE_UNSUPPORTED_DT);
VDISPATCH_REORDER_IC(
simple_attr_check(attr, true, false), VERBOSE_UNSUPPORTED_ATTR);
VDISPATCH_REORDER_IC(input_d.matches_tag(tag_i),
VERBOSE_UNSUPPORTED_TENSOR_LAYOUT, "src");
VDISPATCH_REORDER_IC(output_d.matches_tag(tag_o),
VERBOSE_UNSUPPORTED_TENSOR_LAYOUT, "dst");
VDISPATCH_REORDER_IC(!req_comp, "compensation is not supported");
VDISPATCH_REORDER_IC(mask_ok(req_asymmetric_comp,
output_d.extra().asymm_compensation_mask),
"zero-points compensation configuration is not supported");
return status::success;
}
GET_SCRATCHPAD_SIZE_ZERO();
static status_t execute(const cpu_reorder_pd_t *pd, const exec_ctx_t &ctx) {
DECLARE_COMMON_PARAMS();
using namespace format_tag;
static constexpr bool w_groups = !utils::one_of(tag_o, Owi16o, Owhi16o);
constexpr int is_1d = utils::one_of(tag_o, Owi16o, gOwi16o);
const bool is_3d = false; // TODO once enabled
constexpr dim_t oc_blksize = 16;
const auto &plain_d = order_keep ? input_d : output_d;
const auto &dims = input_d.dims();
const auto &pdims
= order_keep ? output_d.padded_dims() : input_d.padded_dims();
const dim_t G = w_groups ? dims[0] : 1;
const dim_t OC = dims[w_groups + 0];
const dim_t NB_OC = pdims[w_groups + 0] / oc_blksize;
const dim_t IC = dims[w_groups + 1];
const dim_t D = is_3d ? dims[2 + w_groups] : 1;
const dim_t H = is_1d ? 1 : dims[2 + w_groups + is_3d];
const dim_t W = dims[w_groups + is_3d + 3 - is_1d];
const bool has_asymmetric_comp = output_d.extra().flags
& memory_extra_flags::compensation_conv_asymmetric_src;
float adj_scale
= (output_d.extra().flags & memory_extra_flags::scale_adjust)
? output_d.extra().scale_adjust
: 1.f;
auto ker = [&](const data_t<type_i> *inp, data_t<type_o> *out,
int32_t *zp, const float *s, const float *d,
const dim_t oc_block) {
for (dim_t oc = 0; oc < oc_block; ++oc) {
const auto plain_off
= oc * plain_d.blocking_desc().strides[w_groups + 0];
out[oc] = q10n::qz_b0_t<data_t<type_i>, data_t<type_o>>()(
inp[plain_off], s[oc] * adj_scale * d[oc]);
if (has_asymmetric_comp) zp[oc] -= (int32_t)(out[oc]);
}
// fill memory with '0' in case of padded channel dimensions
for (dim_t oc = oc_block; oc < oc_blksize; ++oc) {
out[oc] = 0;
}
};
size_t offset = output_d.size() - output_d.additional_buffer_size();
int32_t *zp = has_asymmetric_comp
? reinterpret_cast<int32_t *>(output + offset)
: nullptr;
if (has_asymmetric_comp) {
parallel_nd(G * NB_OC * oc_blksize, [&](dim_t i) { zp[i] = 0; });
}
#define wei_blk_off(md, g, o, i, d, h, w) \
(is_1d ? (md).blk_off<!w_groups>(g, o, i, w) \
: is_3d ? (md).blk_off<!w_groups>(g, o, i, d, h, w) \
: (md).blk_off<!w_groups>(g, o, i, h, w))
parallel_nd(G, NB_OC, [&](dim_t g, dim_t O) {
for_(dim_t I = 0; I < IC; I++)
for_(dim_t d = 0; d < D; d++)
for_(dim_t h = 0; h < H; h++)
for (dim_t w = 0; w < W; w++) {
auto i = &input[wei_blk_off(
input_d, g, oc_blksize * O, I, d, h, w)];
auto o = &output[wei_blk_off(output_d, g, O, I, d, h, w)];
const dim_t oc_block
= nstl::min(oc_blksize, OC - O * oc_blksize);
dim_t _offset = (g * NB_OC + O) * oc_blksize;
int32_t *zp_ptr = (order_keep && has_asymmetric_comp)
? &zp[_offset]
: nullptr;
const float *src_scales_ptr
= &src_scales[src_scales_mask == 0 ? 0 : _offset];
const float *dst_scales_ptr
= &dst_scales[dst_scales_mask == 0 ? 0 : _offset];
ker(i, o, zp_ptr, src_scales_ptr, dst_scales_ptr, oc_block);
}
});
#undef wei_blk_off
return status::success;
}
};
/* Asymmetric Blocking */
template <SIMPLE_REORDER_TEMPL_DECL>
struct simple_reorder_impl<SIMPLE_REORDER_TEMPL_CALL,
typename utils::enable_if<(utils::one_of(tag_i, format_tag::iwo,
format_tag::oiw, format_tag::wio)
&& utils::one_of(tag_o,
format_tag::OwI16o4i,
format_tag::OIw16i16o4i))
|| (utils::one_of(
tag_i, format_tag::goiw, format_tag::wigo)
&& utils::one_of(tag_o, format_tag::gOwI16o4i,
format_tag::gOIw16i16o4i))
|| (utils::one_of(tag_i, format_tag::ihwo,
format_tag::hwio, format_tag::oihw)
&& utils::one_of(tag_o, format_tag::OhwI16o4i,
format_tag::OIhw16i16o4i))
|| (utils::one_of(
tag_i, format_tag::goihw, format_tag::hwigo)
&& utils::one_of(tag_o, format_tag::gOhwI16o4i,
format_tag::gOIhw16i16o4i))
|| (utils::one_of(tag_i, format_tag::idhwo,
format_tag::dhwio, format_tag::oidhw)
&& utils::one_of(tag_o, format_tag::OdhwI16o4i,
format_tag::OIdhw16i16o4i))
|| (utils::one_of(tag_i, format_tag::goidhw)
&& utils::one_of(tag_o, format_tag::gOdhwI16o4i,
format_tag::gOIdhw16i16o4i)),
spec::conv_req_comp>::type> {
static status_t is_applicable(const memory_desc_wrapper &input_d,
const memory_desc_wrapper &output_d, const primitive_attr_t *attr) {
using namespace format_tag;
using namespace data_type;
using namespace utils;
VDISPATCH_REORDER_IC(!input_d.has_runtime_dims_or_strides(),
VERBOSE_RUNTIMEDIM_UNSUPPORTED);
int src_scales_mask, dst_scales_mask;
CHECK(get_scales_mask(attr, &src_scales_mask, &dst_scales_mask));
int scales_mask = std::max(src_scales_mask, dst_scales_mask);
static constexpr bool w_groups = !one_of(tag_o, OwI16o4i, OIw16i16o4i,
OhwI16o4i, OIhw16i16o4i, OdhwI16o4i, OIdhw16i16o4i);
// Current formats are only used in jit kernels that natively
// support s8 instructions, hence, there is no need for signed
// compensation.
const bool req_comp = output_d.extra().flags
& memory_extra_flags::compensation_conv_s8s8;
const bool req_asymmetric_comp = output_d.extra().flags
& memory_extra_flags::compensation_conv_asymmetric_src;
auto mask_ok = [&](bool check, int mask) {
return IMPLICATION(check, mask == (w_groups ? 0x3 : 0x1));
};
VDISPATCH_REORDER_IC(one_of(input_d.data_type(), f32, s8, bf16),
VERBOSE_UNSUPPORTED_DT);
VDISPATCH_REORDER_IC(
output_d.data_type() == s8, VERBOSE_UNSUPPORTED_DT);
VDISPATCH_REORDER_IC(
simple_attr_check(attr, true, false), VERBOSE_UNSUPPORTED_ATTR);
VDISPATCH_REORDER_IC(input_d.matches_tag(tag_i),
VERBOSE_UNSUPPORTED_TENSOR_LAYOUT, "src");
VDISPATCH_REORDER_IC(output_d.matches_tag(tag_o),
VERBOSE_UNSUPPORTED_TENSOR_LAYOUT, "dst");
VDISPATCH_REORDER_IC(!req_comp, "compensation is not supported");
VDISPATCH_REORDER_IC(mask_ok(req_asymmetric_comp,
output_d.extra().asymm_compensation_mask),
"zero-points compensation configuration is not supported");
VDISPATCH_REORDER_IC(
IMPLICATION(!w_groups, one_of(scales_mask, 0, 0x1)),
VERBOSE_UNSUPPORTED_SCALES_CFG);
VDISPATCH_REORDER_IC(IMPLICATION(w_groups, one_of(scales_mask, 0, 0x3)),
VERBOSE_UNSUPPORTED_SCALES_CFG);
return status::success;
}
GET_SCRATCHPAD_SIZE_ZERO();
static status_t execute(const cpu_reorder_pd_t *pd, const exec_ctx_t &ctx) {
DECLARE_COMMON_PARAMS();
using namespace format_tag;
static constexpr bool w_groups
= !utils::one_of(tag_o, OwI16o4i, OIw16i16o4i, OhwI16o4i,
OIhw16i16o4i, OdhwI16o4i, OIdhw16i16o4i);
constexpr int is_1d = utils::one_of(
tag_o, OwI16o4i, gOwI16o4i, OIw16i16o4i, gOIw16i16o4i);
const bool is_3d = utils::one_of(
tag_o, OdhwI16o4i, gOdhwI16o4i, OIdhw16i16o4i, gOIdhw16i16o4i);
constexpr dim_t oc_blksize = 16;
constexpr dim_t ic_blksize
= utils::one_of(tag_traits_t<tag_o>::inner_blks, ib::_16b16a4b,
ib::_16c16b4c)
? 64
: utils::one_of(tag_traits_t<tag_o>::inner_blks, ib::_16a4b,
ib::_16b4c)
? 4
: 1;
assert(ic_blksize != 1);
const auto &plain_d = order_keep ? input_d : output_d;
const auto &dims = input_d.dims();
const auto &pdims
= order_keep ? output_d.padded_dims() : input_d.padded_dims();
const dim_t G = w_groups ? dims[0] : 1;
const dim_t OC = dims[w_groups + 0];
const dim_t NB_OC = pdims[w_groups + 0] / oc_blksize;
const dim_t IC = dims[w_groups + 1];
const dim_t NB_IC = pdims[w_groups + 1] / ic_blksize;
const dim_t D = is_3d ? dims[2 + w_groups] : 1;
const dim_t H = is_1d ? 1 : dims[2 + w_groups + is_3d];
const dim_t W = dims[w_groups + is_3d + 3 - is_1d];
const bool has_asymmetric_comp = output_d.extra().flags
& memory_extra_flags::compensation_conv_asymmetric_src;
float adj_scale
= (output_d.extra().flags & memory_extra_flags::scale_adjust)
? output_d.extra().scale_adjust
: 1.f;
// This kernel is used primarily for tensors with multiple inner
// blocks for which generic zero padding must be used.
// TODO: apply zero padding inside parallel_nd()
ctx.zero_pad_output(DNNL_ARG_TO);
auto ker = [&](const data_t<type_i> *inp, data_t<type_o> *out,
int32_t *zp, const float *s, const float *d,
const dim_t oc_block, const dim_t ic_block) {
for_(dim_t ic = 0; ic < ic_block; ++ic)
for (dim_t oc = 0; oc < oc_block; ++oc) {
const auto plain_off
= oc * plain_d.blocking_desc().strides[w_groups + 0]
+ ic * plain_d.blocking_desc().strides[w_groups + 1];
auto index = AB_or_BC_blk_off<tag_traits_t<tag_o>::inner_blks>(
oc, ic);
out[index] = q10n::qz_b0_t<data_t<type_i>, data_t<type_o>>()(
inp[plain_off], s[oc] * adj_scale * d[oc]);
if (has_asymmetric_comp) zp[oc] -= (int32_t)(out[index]);
}
};
size_t offset = output_d.size() - output_d.additional_buffer_size();
int32_t *zp = has_asymmetric_comp
? reinterpret_cast<int32_t *>(output + offset)
: nullptr;
if (has_asymmetric_comp) {
parallel_nd(G * NB_OC * oc_blksize, [&](dim_t i) { zp[i] = 0; });
}
#define wei_blk_off(md, g, o, i, d, h, w) \
(is_1d ? (md).blk_off<!w_groups>(g, o, i, w) \
: is_3d ? (md).blk_off<!w_groups>(g, o, i, d, h, w) \
: (md).blk_off<!w_groups>(g, o, i, h, w))
parallel_nd(G, NB_OC, [&](dim_t g, dim_t O) {
for_(dim_t I = 0; I < NB_IC; I++)
for_(dim_t d = 0; d < D; d++)
for_(dim_t h = 0; h < H; h++)
for (dim_t w = 0; w < W; w++) {
auto i = &input[wei_blk_off(
input_d, g, oc_blksize * O, ic_blksize * I, d, h, w)];
auto o = &output[wei_blk_off(output_d, g, O, I, d, h, w)];
const dim_t oc_block
= nstl::min(oc_blksize, OC - O * oc_blksize);
const dim_t ic_block
= nstl::min(ic_blksize, IC - I * ic_blksize);
dim_t _offset = (g * NB_OC + O) * oc_blksize;
int32_t *zp_ptr = (order_keep && has_asymmetric_comp)
? &zp[_offset]
: nullptr;
const float *src_scales_ptr
= &src_scales[src_scales_mask == 0 ? 0 : _offset];
const float *dst_scales_ptr
= &dst_scales[dst_scales_mask == 0 ? 0 : _offset];
ker(i, o, zp_ptr, src_scales_ptr, dst_scales_ptr, oc_block,
ic_block);
}
});
#undef wei_blk_off
return status::success;
}
};
template <SIMPLE_REORDER_TEMPL_DECL>
struct simple_reorder_impl<SIMPLE_REORDER_TEMPL_CALL,
typename utils::enable_if<
(utils::one_of(tag_i, format_tag::ab, format_tag::ba,
format_tag::abc, format_tag::acb)
&& utils::one_of(tag_o, format_tag::BA16a16b4a,
format_tag::BA16a32b4a, format_tag::BA16a48b4a,
format_tag::BA16a64b4a, format_tag::aCB16b16c4b,
format_tag::aCB16b32c4b,
format_tag::aCB16b48c4b,
format_tag::aCB16b64c4b)),
spec::conv_req_comp>::type> {
static status_t is_applicable(const memory_desc_wrapper &input_d,
const memory_desc_wrapper &output_d, const primitive_attr_t *attr) {
using namespace format_tag;
using namespace data_type;
using namespace utils;
VDISPATCH_REORDER_IC(!input_d.has_runtime_dims_or_strides(),
VERBOSE_RUNTIMEDIM_UNSUPPORTED);
int src_scales_mask, dst_scales_mask;
CHECK(get_scales_mask(attr, &src_scales_mask, &dst_scales_mask));
int scales_mask = std::max(src_scales_mask, dst_scales_mask);
const size_t D_mask
= array_product(input_d.dims(), math::ilog2q(scales_mask + 1));
const bool req_comp = output_d.extra().flags
& memory_extra_flags::compensation_conv_s8s8;
const bool req_asymmetric_comp = output_d.extra().flags
& memory_extra_flags::compensation_conv_asymmetric_src;
const auto ndims = input_d.ndims();
auto mask_ok = [&](bool check, int mask) {
return IMPLICATION(
check, mask == (1 << ndims) - 1 - (1 << (ndims - 2)));
};
VDISPATCH_REORDER_IC(one_of(input_d.data_type(), f32, s8, bf16, f16,
f8_e5m2, f8_e4m3),
VERBOSE_UNSUPPORTED_DT);
VDISPATCH_REORDER_IC(