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brgemm_matmul_utils.cpp
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/*******************************************************************************
* Copyright 2021-2025 Intel Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include <unordered_set>
#include "common/dnnl_thread.hpp"
#include "cpu/binary_injector_utils.hpp"
#include "cpu/matmul/gemm_based_common.hpp"
#include "cpu/matmul/matmul_utils.hpp"
#include "cpu/platform.hpp"
#include "cpu/x64/injectors/jit_uni_postops_injector.hpp"
#include "cpu/x64/matmul/amx_blocking_heuristics.hpp"
#include "cpu/x64/matmul/brgemm_matmul_utils.hpp"
#include "oneapi/dnnl/dnnl_debug.h"
// TODO add a method to print brgemm conf info
#define VCONDCHECK_BG(cond, msg, ...) \
VCONDCHECK(primitive, create, dispatch, brgemm_matmul, (cond), \
status::unimplemented, msg, ##__VA_ARGS__);
#define VCHECK_BG(f, msg, ...) \
VCHECK(primitive, create, dispatch, brgemm_matmul, f, msg, ##__VA_ARGS__);
namespace dnnl {
namespace impl {
namespace cpu {
namespace x64 {
namespace matmul {
using namespace dnnl::impl::cpu::matmul;
using namespace dnnl::impl::memory_tracking::names;
using namespace dnnl::impl::utils;
using namespace data_type;
using namespace format_tag;
int get_n_block_from_tag(format_tag_t matrix_b_tag) {
// Note: consider using weights mem_descriptor 'inner_blks' to
// return B's inner block for non-default cases.
switch (matrix_b_tag) {
case aCB16b64c:
case aCB16b64c2b:
case aCB16b64c4b:
case BA16a64b4a:
case BA16a64b2a:
case BA16a64b: return 64;
case aCB16b48c:
case aCB16b48c2b:
case aCB16b48c4b:
case BA16a48b:
case BA16a48b2a:
case BA16a48b4a: return 48;
case aCB16b32c:
case aCB16b32c2b:
case aCB16b32c4b:
case BA16a32b:
case BA16a32b2a:
case BA16a32b4a: return 32;
case aCB2b24c:
case BA8a24b: return 24;
case aCB16b16c:
case aCB16b16c2b:
case aCB16b16c4b:
case BA16a16b:
case BA16a16b2a:
case BA16a16b4a: return 16;
case aCB2b8c:
case BA8a8b: return 8;
default: return 0;
}
}
// TODO: add support of post-ops with multiple binary and eltwise execution
bool post_ops_ok(brgemm_matmul_conf_t &bgmmc, const primitive_attr_t &attr,
const memory_desc_wrapper &dst_d,
bool limit_bcast_strategies_set = false) {
using namespace injector;
const auto &post_ops = attr.post_ops_;
const auto ndims = dst_d.ndims();
bool is_binary_po_per_oc_sp_bcast {};
bool is_binary_po_per_oc_d_bcast {};
bool is_binary_po_channel_bcast {};
bool is_binary_po_per_mb_bcast {};
bool is_binary_po_per_mb_w_bcast {};
bool is_binary_po_per_w_bcast {};
bool is_binary_po_batch_bcast {};
std::tie(is_binary_po_per_oc_sp_bcast, is_binary_po_per_oc_d_bcast,
is_binary_po_channel_bcast, is_binary_po_per_mb_bcast,
is_binary_po_per_mb_w_bcast, is_binary_po_per_w_bcast,
is_binary_po_batch_bcast)
= binary_injector_utils::bcast_strategies_present_tup(
post_ops.entry_, dst_d,
broadcasting_strategy_t::per_oc_spatial,
broadcasting_strategy_t::per_oc_d,
broadcasting_strategy_t::per_mb,
broadcasting_strategy_t::per_mb_spatial,
broadcasting_strategy_t::per_mb_w,
broadcasting_strategy_t::per_w,
broadcasting_strategy_t::batch);
const bool supported_binary_bcast
= IMPLICATION(is_binary_po_per_oc_sp_bcast, ndims < 4)
&& IMPLICATION(is_binary_po_per_oc_d_bcast, ndims == 4)
&& IMPLICATION(
is_binary_po_channel_bcast, utils::one_of(ndims, 3, 4))
&& IMPLICATION(
is_binary_po_per_mb_w_bcast, utils::one_of(ndims, 3, 4))
&& IMPLICATION(is_binary_po_per_w_bcast, utils::one_of(ndims, 3, 4))
&& IMPLICATION(
is_binary_po_per_mb_bcast, utils::one_of(ndims, 3, 4))
&& IMPLICATION(
is_binary_po_batch_bcast, utils::one_of(ndims, 3, 4));
const bcast_set_t default_bcast_set = {broadcasting_strategy_t::per_oc,
broadcasting_strategy_t::per_oc_spatial,
broadcasting_strategy_t::per_oc_d, broadcasting_strategy_t::scalar,
broadcasting_strategy_t::per_mb,
broadcasting_strategy_t::per_mb_spatial,
broadcasting_strategy_t::per_mb_w, broadcasting_strategy_t::per_w,
broadcasting_strategy_t::batch,
broadcasting_strategy_t::no_broadcast};
const bcast_set_t limited_bcast_set = {broadcasting_strategy_t::scalar,
broadcasting_strategy_t::no_broadcast};
const bcast_set_t bcast_set
= limit_bcast_strategies_set || bgmmc.is_runtime_N
? limited_bcast_set
: default_bcast_set;
// binary post-ops are disabled for runtime N due to issues in
// injector::post_ops_ok() with identification of per_oc strategy
// for some cases
std::vector<post_op_type> accepted_post_ops;
accepted_post_ops.push_back(sum);
accepted_post_ops.push_back(eltwise);
if (!bgmmc.is_runtime_N) accepted_post_ops.push_back(binary);
return supported_binary_bcast
&& injector::post_ops_ok(
post_ops_ok_args_t(get_max_cpu_isa(), accepted_post_ops,
post_ops, &dst_d, false /*sum_at_pos_0_only*/,
false /*sum_requires_scale_one*/,
false /*sum_requires_zp_zero*/,
true /*sum_requires_same_params*/, bcast_set));
}
// Trivial: The motivation is to compute batch offset for a memory
// (src or wei or dst) with minimal overhead, by using
// `batch_offset = b * b_stride`.
// This is possible when the batch layout is contiguous.
bool is_batch_layout_trivial(
const memory_desc_wrapper &mdw, const dim_t batch) {
const int ndims = mdw.ndims();
if (ndims <= 3) return true;
const auto &strides = mdw.strides();
const int batch_start_idx = ndims - 3;
dim_t cur_stride = strides[batch_start_idx];
dim_t min_batch_stride = cur_stride;
dim_t max_batch_stride = cur_stride;
for (int d = batch_start_idx - 1; d >= 0; --d) {
cur_stride = strides[d];
min_batch_stride = nstl::min(min_batch_stride, cur_stride);
max_batch_stride = nstl::max(max_batch_stride, cur_stride);
}
if (min_batch_stride == 0) return false;
return max_batch_stride / min_batch_stride == batch;
}
status_t check_isa_with_datatype(
const cpu_isa_t isa, const brgemm_matmul_conf_utils_t &bm_conf_utils) {
const bool ok
= IMPLICATION(bm_conf_utils.is_f32(),
one_of(isa, avx512_core, avx2) || bm_conf_utils.is_bf32())
&& IMPLICATION(bm_conf_utils.is_int8(),
is_superset(isa, avx512_core)
|| is_superset(isa, avx2_vnni))
&& IMPLICATION(bm_conf_utils.is_bf16(),
one_of(isa, avx512_core_amx, avx512_core_bf16, avx2_vnni_2))
&& IMPLICATION(bm_conf_utils.is_f16(),
one_of(isa, avx512_core_amx_fp16, avx512_core_fp16,
avx2_vnni_2))
// `avx512_core_amx_fp16` is not supported for plain upconversion
// as HW supports native compute.
&& IMPLICATION(bm_conf_utils.is_f32_f16(),
one_of(isa, avx512_core_fp16, avx2_vnni_2, avx512_core,
avx2))
// `avx512_core_amx` is not supported for plain upconversion as HW
// supports native compute.
&& IMPLICATION(bm_conf_utils.is_f32_bf16(),
one_of(isa, avx512_core_bf16, avx2_vnni_2, avx512_core,
avx2))
&& IMPLICATION(bm_conf_utils.is_int8_with_bf16_dst(),
is_superset(isa, avx512_core) || isa == avx2_vnni_2)
&& IMPLICATION(bm_conf_utils.is_bf16_with_int_wei(),
is_superset(isa, avx512_core_bf16))
&& IMPLICATION(bm_conf_utils.is_f16_with_int_wei(),
one_of(isa, avx512_core_amx_fp16, avx512_core_fp16))
&& IMPLICATION(bm_conf_utils.is_f8(),
is_superset(isa, avx512_core_amx_fp16));
return ok ? status::success : status::unimplemented;
}
status_t check_datatype_cfg(const brgemm_matmul_conf_utils_t &bm_conf_utils) {
const bool ok
= one_of(true, bm_conf_utils.is_f32(), bm_conf_utils.is_bf16(),
bm_conf_utils.is_f16(), bm_conf_utils.is_f32_f16(),
bm_conf_utils.is_f32_bf16(), bm_conf_utils.is_bf32(),
bm_conf_utils.is_f8(), bm_conf_utils.is_int8(),
bm_conf_utils.is_bf16_with_int_wei(),
bm_conf_utils.is_f16_with_int_wei())
&& IMPLICATION(bm_conf_utils.is_bf16_with_int_wei()
|| bm_conf_utils.is_f16_with_int_wei(),
bm_conf_utils.with_weights_decompression());
return ok ? status::success : status::unimplemented;
}
brgemm_matmul_conf_utils_t::brgemm_matmul_conf_utils_t(
brgemm_matmul_conf_t &bgmmc, const cpu_isa_t isa,
const primitive_attr_t &attr, bool A_any_layout, bool B_any_layout,
bool C_any_layout, bool bias_any_layout)
: bgmmc(bgmmc)
, f32_dt(utils::everyone_is(f32, bgmmc.src_dt, bgmmc.wei_dt, bgmmc.dst_dt))
, bf16_dt(utils::everyone_is(bf16, bgmmc.src_dt, bgmmc.wei_dt)
&& one_of(bgmmc.dst_dt, bf16, f32))
, f16_dt(utils::everyone_is(f16, bgmmc.src_dt, bgmmc.wei_dt)
&& one_of(bgmmc.dst_dt, f16, f32))
, f8_dt(one_of(bgmmc.src_dt, f8_e5m2, f8_e4m3)
&& one_of(bgmmc.wei_dt, f8_e5m2, f8_e4m3)
&& one_of(bgmmc.dst_dt, f16, f32, bf16, f8_e5m2, f8_e4m3))
, int8_dt(utils::one_of(bgmmc.src_dt, u8, s8) && bgmmc.wei_dt == s8
&& one_of(bgmmc.dst_dt, u8, s8, s32, f32, bf16))
, bf32_dt(f32_dt
&& one_of(attr.fpmath_.mode_, fpmath_mode::bf16, fpmath_mode::any)
&& isa == avx512_core_amx)
, weights_decompression_support(one_of(bgmmc.wei_dt, u8, s8, u4, s4)
&& one_of(attr.fpmath_.mode_, fpmath_mode::bf16, fpmath_mode::f16,
fpmath_mode::any)
&& IMPLICATION(attr.fpmath_.mode_ == fpmath_mode::f16,
bgmmc.src_dt == f16)
&& IMPLICATION(attr.fpmath_.mode_ == fpmath_mode::bf16,
bgmmc.src_dt == bf16)
&& attr.fpmath_.apply_to_int_)
, bf16_with_int_wei_dt(weights_decompression_support && bgmmc.src_dt == bf16
&& one_of(bgmmc.dst_dt, bf16, f32))
// Keep this var separate from f16_dt to not slip f16:f16 on avx512_core and
// avx2 as there's no kernel for such combination.
, f32_f16_dt(bgmmc.src_dt == f32 && bgmmc.wei_dt == f16
&& one_of(bgmmc.dst_dt, f16, f32))
// Keep this var separate from bf16_dt to not slip bf16:bf16 on avx512_core
// and avx2 as there's no kernel for such combination.
, f32_bf16_dt(bgmmc.src_dt == f32 && bgmmc.wei_dt == bf16
&& one_of(bgmmc.dst_dt, bf16, f32))
, f16_with_int_wei_dt(weights_decompression_support && bgmmc.src_dt == f16
&& one_of(bgmmc.dst_dt, f16, f32))
, A_any_layout(A_any_layout)
, B_any_layout(B_any_layout)
, C_any_layout(C_any_layout)
, bias_any_layout(bias_any_layout)
, plain_tensor_layout_tag(utils::pick(bgmmc.ndims - 2, ab, abc, abcd, abcde,
abcdef, abcdefg, abcdefgh, abcdefghi, abcdefghij, abcdefghijk,
abcdefghijkl))
, transposed_tensor_layout_tag(utils::pick(bgmmc.ndims - 2, ba, acb, abdc,
abced, abcdfe, abcdegf, abcdefhg, abcdefgih, abcdefghji,
abcdefghikj, abcdefghijlk))
, blocked_64n_B_layout_tag(pick_blocked_B_layout(64))
, blocked_48n_B_layout_tag(pick_blocked_B_layout(48))
, blocked_32n_B_layout_tag(pick_blocked_B_layout(32))
, blocked_24n_B_layout_tag(pick_blocked_B_layout(24))
, blocked_16n_B_layout_tag(pick_blocked_B_layout(16))
, blocked_8n_B_layout_tag(pick_blocked_B_layout(8))
, blocked_B_layouts_allowed(IMPLICATION(is_f32(),
!utils::one_of(format_tag::undef,
blocked_64n_B_layout_tag,
blocked_48n_B_layout_tag,
blocked_32n_B_layout_tag,
blocked_24n_B_layout_tag,
blocked_16n_B_layout_tag,
blocked_8n_B_layout_tag))
&& IMPLICATION(!is_f32(),
!utils::one_of(format_tag::undef,
blocked_64n_B_layout_tag,
blocked_48n_B_layout_tag,
blocked_32n_B_layout_tag,
blocked_16n_B_layout_tag)))
, n_blk_fixed((!B_any_layout) && blocked_B_layouts_allowed)
, isa_(isa) {}
int brgemm_matmul_conf_utils_t::get_default_n_block(
format_tag_t matrix_b_tag) const {
const int n_blk = get_n_block_from_tag(matrix_b_tag);
if (n_blk > 0) return n_blk;
const int simd_w = isa_max_vlen(isa_) / sizeof(float);
if (matmul_amx_blocking_params_macro_t::is_supported(bgmmc, *this)) {
return 32;
}
return is_superset(isa_, avx512_core) || !f32_dt
? 64
: nstl::min<int>(24, rnd_up(bgmmc.N, simd_w));
}
status_t brgemm_matmul_conf_utils_t::set_or_check_B_tag(memory_desc_t &B_md,
const matmul_helper_t &helper, bool init_n_tag) const {
const memory_desc_wrapper B_d(&B_md);
if (B_any_layout) {
const int default_n_block = init_n_tag
? get_default_n_block(format_tag::undef)
: bgmmc.N_blk;
bgmmc.wei_tag = blocked_B_layouts_allowed && !bgmmc.is_runtime_N
&& !bgmmc.is_int4_weights
? this->pick_blocked_B_layout(default_n_block)
: plain_tensor_layout_tag;
VCONDCHECK_BG(
format_tag::undef != bgmmc.wei_tag, VERBOSE_UNSUPPORTED_TAG)
VCHECK_BG(memory_desc_init_by_tag(B_md, bgmmc.wei_tag),
VERBOSE_UNSUPPORTED_TAG);
const int dmax = nstl::min(bgmmc.ndims, 3);
for (int d = 0; d < dmax; d++) {
int dim = bgmmc.ndims - 1 - d;
bgmmc.B_strides[d]
= bgmmc.b_dt_sz * B_d.blocking_desc().strides[dim];
}
} else {
bgmmc.wei_tag = blocked_B_layouts_allowed && !bgmmc.is_runtime_N
&& !bgmmc.is_int4_weights
? memory_desc_matches_one_of_tag(B_md, plain_tensor_layout_tag,
transposed_tensor_layout_tag, blocked_64n_B_layout_tag,
blocked_48n_B_layout_tag, blocked_32n_B_layout_tag,
blocked_16n_B_layout_tag)
: memory_desc_matches_one_of_tag(B_md, plain_tensor_layout_tag,
transposed_tensor_layout_tag, acbd, adbc);
if (bgmmc.wei_tag == format_tag::undef) {
if (gemm_based::check_gemm_input_format(B_md)) {
// Note: Here we batch layout may not be accurately represented
// by the wei_tag string, due to all the permutations of the
// batch. Only the gemm dimensions "n, k" are accurately
// represented in the string representing transposed or not.
bgmmc.wei_tag = helper.transB() == 'N'
? plain_tensor_layout_tag
: transposed_tensor_layout_tag;
}
}
VCONDCHECK_BG(
format_tag::undef != bgmmc.wei_tag, VERBOSE_UNSUPPORTED_TAG)
}
return status::success;
}
status_t brgemm_matmul_conf_utils_t::update_and_check_B_tag(memory_desc_t &B_md,
int n_blk_size, const matmul_helper_t &helper) const {
if (n_blk_fixed && n_blk_size != bgmmc.wei_n_blk)
return status::unimplemented;
if (!(B_any_layout && blocked_B_layouts_allowed)) return status::success;
return set_or_check_B_tag(B_md, helper, false);
}
status_t brgemm_matmul_conf_utils_t::set_or_check_tags(memory_desc_t &A_md,
memory_desc_t &C_md, memory_desc_t &bias_md,
const matmul_helper_t &helper) const {
if (A_any_layout) {
const format_tag_t desired_A_tag = plain_tensor_layout_tag;
VCHECK_BG(memory_desc_init_by_tag(A_md, desired_A_tag),
VERBOSE_UNSUPPORTED_TAG);
bgmmc.src_tag = desired_A_tag;
} else {
const bool xf16_avx2_vnni_2 = (this->is_bf16() || this->is_f16())
&& bgmmc.isa == avx2_vnni_2;
const bool is_int8_avx512_core
= this->is_int8() && is_superset(bgmmc.isa, avx512_core);
const bool is_adbc_allowed
= (this->is_bf16() || this->is_f32() || this->is_bf32()
|| this->is_f16() || this->is_f32_f16()
|| this->is_f32_bf16() || this->is_bf16_with_int_wei()
|| this->is_f16_with_int_wei())
&& !xf16_avx2_vnni_2;
bgmmc.src_tag = is_adbc_allowed
? memory_desc_matches_one_of_tag(A_md, plain_tensor_layout_tag,
transposed_tensor_layout_tag, acbd, adbc)
: is_int8_avx512_core
? memory_desc_matches_one_of_tag(A_md, plain_tensor_layout_tag,
transposed_tensor_layout_tag, acbd)
: memory_desc_matches_one_of_tag(
A_md, plain_tensor_layout_tag, acbd);
if (bgmmc.src_tag == format_tag::undef
|| (memory_desc_matches_tag(A_md, transposed_tensor_layout_tag)
&& memory_desc_matches_tag(
A_md, plain_tensor_layout_tag)
&& IMPLICATION(
!is_adbc_allowed, is_int8_avx512_core))) {
if (gemm_based::check_gemm_input_format(A_md)) {
// Note: Here we batch layout may not be accurately represented
// by the wei_tag string, due to all the permutations of the
// batch. Only the gemm dimensions "m, k" are accurately
// represented in the string representing transposed or not.
bgmmc.src_tag = helper.transA() == 'N'
? plain_tensor_layout_tag
: transposed_tensor_layout_tag;
}
if (!IMPLICATION(bgmmc.src_tag == transposed_tensor_layout_tag,
is_adbc_allowed || is_int8_avx512_core))
bgmmc.src_tag = format_tag::undef;
}
}
if (C_any_layout) {
const format_tag_t desired_C_tag = plain_tensor_layout_tag;
VCHECK_BG(memory_desc_init_by_tag(C_md, desired_C_tag),
VERBOSE_UNSUPPORTED_TAG);
bgmmc.dst_tag = desired_C_tag;
} else {
const memory_desc_wrapper C_mdw(C_md);
// If one of dims is `1` then `ba` is identical to `ab`.
format_tag_t allowed_transposed_tensor_layout_tag
= C_mdw.ndims() == 2 && C_mdw.count_non_unit_dims(1)
? ba
: plain_tensor_layout_tag;
bgmmc.dst_tag
= memory_desc_matches_one_of_tag(C_md, plain_tensor_layout_tag,
allowed_transposed_tensor_layout_tag, acbd);
if (bgmmc.dst_tag == format_tag::undef) {
if (gemm_based::check_gemm_output_format(C_md)) {
// Note: Here we batch layout may not be accurately represented
// by the wei_tag string, due to all the permutations of the
// batch. Only the gemm dimensions "m, n" are accurately
// represented in the string.
bgmmc.dst_tag = plain_tensor_layout_tag;
}
}
}
VCONDCHECK_BG(!one_of(format_tag::undef, bgmmc.src_tag, bgmmc.dst_tag),
VERBOSE_UNSUPPORTED_TAG)
if (bgmmc.with_bias && bias_any_layout)
VCHECK_BG(memory_desc_init_by_tag(bias_md, plain_tensor_layout_tag),
VERBOSE_UNSUPPORTED_TAG);
return status::success;
}
status_t brgemm_matmul_conf_utils_t::set_B_flags(memory_desc_t &B_md) const {
memory_desc_t want_B_md = B_md;
// Set bits for all dimensions except k dimension
const int compensation_mask
= ((1 << bgmmc.ndims) - 1 - (1 << (bgmmc.ndims - 2)));
if (bgmmc.s8s8_compensation_required && bgmmc.blocked_B) {
want_B_md.extra.flags |= memory_extra_flags::compensation_conv_s8s8;
want_B_md.extra.compensation_mask = compensation_mask;
}
if (bgmmc.src_zp_type != brgemm_broadcast_t::none && bgmmc.blocked_B) {
want_B_md.extra.flags
|= memory_extra_flags::compensation_conv_asymmetric_src;
want_B_md.extra.asymm_compensation_mask = compensation_mask;
}
if (B_any_layout) {
B_md = want_B_md;
return status::success;
}
return B_md == want_B_md ? status::success : status::unimplemented;
}
format_tag_t brgemm_matmul_conf_utils_t::pick_blocked_B_layout(
int n_blk) const {
if (bgmmc.ndims > 3) return format_tag::undef;
if (this->is_int8() || this->is_f8()) switch (n_blk) {
case 64: return bgmmc.ndims == 3 ? aCB16b64c4b : BA16a64b4a;
case 48: return bgmmc.ndims == 3 ? aCB16b48c4b : BA16a48b4a;
case 32: return bgmmc.ndims == 3 ? aCB16b32c4b : BA16a32b4a;
case 16: return bgmmc.ndims == 3 ? aCB16b16c4b : BA16a16b4a;
default: return format_tag::undef;
}
if (this->is_bf16() || this->is_bf16_with_int_wei()
|| ((this->is_f16() || this->is_f32_f16() || this->is_f32_bf16()
|| this->is_f16_with_int_wei())
&& (is_superset(bgmmc.isa, avx512_core_amx)
|| is_superset(bgmmc.isa, avx2_vnni_2))))
switch (n_blk) {
case 64: return bgmmc.ndims == 3 ? aCB16b64c2b : BA16a64b2a;
case 48: return bgmmc.ndims == 3 ? aCB16b48c2b : BA16a48b2a;
case 32: return bgmmc.ndims == 3 ? aCB16b32c2b : BA16a32b2a;
case 16: return bgmmc.ndims == 3 ? aCB16b16c2b : BA16a16b2a;
default: return format_tag::undef;
}
// Note: bf32 assumes f32 blocking
if (this->is_f32() || this->is_bf32() || this->is_f16()
|| this->is_f32_f16() || this->is_f32_bf16()
|| this->is_f16_with_int_wei())
switch (n_blk) {
case 64: return bgmmc.ndims == 3 ? aCB16b64c : BA16a64b;
case 48: return bgmmc.ndims == 3 ? aCB16b48c : BA16a48b;
case 32: return bgmmc.ndims == 3 ? aCB16b32c : BA16a32b;
case 24: return bgmmc.ndims == 3 ? aCB8b24c : BA8a24b;
case 16:
return bgmmc.wei_k_blk == 8
? (bgmmc.ndims == 3 ? aCB8b16c : BA8a16b)
: (bgmmc.ndims == 3 ? aCB16b16c : BA16a16b);
case 8: return bgmmc.ndims == 3 ? aCB8b8c : BA8a8b;
default: return format_tag::undef;
}
return format_tag::undef;
}
brgemm_broadcast_t get_zp_type(const primitive_attr_t &attr, int arg) {
return attr.zero_points_.has_default_values(arg)
? brgemm_broadcast_t::none
: brgemm_broadcast_t::per_tensor;
}
struct matmul_avx512_blocking_params_t {
struct matmul_params_t {
matmul_params_t(int m, int n, int k, int od)
: M(m), N(n), K(k), batch(od) {}
const int M;
const int N;
const int K;
const int batch;
};
matmul_avx512_blocking_params_t(const matmul_params_t &m, const int nthr)
: mp(m)
, m_chunks(1)
, m_blk(1)
, m_tail(0)
, n_chunks(1)
, n_blk(1)
, n_tail(0)
, batch_size(1)
, k_blk(1)
, k_tail(0)
, nthr_k(1)
, nthr(nthr) {}
matmul_avx512_blocking_params_t &operator=(
const matmul_avx512_blocking_params_t &brgemm_params) {
m_chunks = brgemm_params.m_chunks;
m_blk = brgemm_params.m_blk;
m_tail = brgemm_params.m_tail;
n_chunks = brgemm_params.n_chunks;
n_blk = brgemm_params.n_blk;
n_tail = brgemm_params.n_tail;
batch_size = brgemm_params.batch_size;
k_blk = brgemm_params.k_blk;
k_tail = brgemm_params.k_tail;
nthr_k = brgemm_params.nthr_k;
return *this;
}
const matmul_params_t ∓
int m_chunks, m_blk, m_tail;
int n_chunks, n_blk, n_tail;
int batch_size, k_blk, k_tail;
int nthr_k;
const int nthr;
void update_params(int m_chunks_, int m_blk_, int n_chunks_, int n_blk_,
int batch_size_, int k_blk_, int nthr_k_) {
m_chunks = m_chunks_;
m_blk = m_blk_;
m_tail = mp.M % m_blk;
n_chunks = n_chunks_;
n_blk = n_blk_;
n_tail = mp.N % n_blk;
batch_size = batch_size_;
k_blk = k_blk_;
k_tail = mp.K % k_blk;
nthr_k = nthr_k_;
}
float calculate_spatial_disbalance(size_t work, size_t thread_block) const {
size_t mod = work % thread_block;
size_t scalar = work < thread_block
? thread_block - mod
: nstl::min(thread_block - mod, mod);
return static_cast<float>(scalar) / thread_block;
}
float get_imbalance() const {
const size_t cur_nthr = nthr / nthr_k;
size_t parallel_work = get_parallel_work();
const float parallel_work_disb
= calculate_spatial_disbalance(parallel_work, cur_nthr);
int m_work = (m_blk * div_up(mp.M, m_blk)) % mp.M;
const float m_blk_disbalance = static_cast<float>(m_work) / mp.M;
int num_n_blk = div_up(mp.N, n_blk);
int par_n_chunks = div_up(num_n_blk, n_chunks);
const float n_chunk_disbalance
= (static_cast<float>(par_n_chunks) * n_chunks - num_n_blk)
/ num_n_blk;
const float disbalance_nthr_k
= calculate_spatial_disbalance(mp.K, nthr_k * k_blk);
const float thread_allocation_disb
= (cur_nthr * nthr_k) != static_cast<size_t>(nthr)
? (static_cast<float>(nthr) - cur_nthr * nthr_k) / nthr
: 0;
const float score
= (parallel_work_disb + m_blk_disbalance + n_chunk_disbalance
+ thread_allocation_disb + disbalance_nthr_k)
/ 5;
return score;
}
size_t get_parallel_work() const {
int m_elems = div_up(mp.M, m_blk * m_chunks);
int n_elems = div_up(mp.N, n_blk * n_chunks);
return static_cast<size_t>(m_elems) * n_elems * mp.batch;
}
inline dim_t get_actual_lda(bool use_buffer_a, dim_t a_dt_sz) const {
if (!use_buffer_a) return mp.K;
constexpr int bytes_in_cacheline = 64;
const int elems_in_cacheline = bytes_in_cacheline / a_dt_sz;
dim_t lda = rnd_up(k_blk, elems_in_cacheline);
const bool is_big_pow_2 = lda >= 512 && math::is_pow2(lda);
if (is_big_pow_2) lda += elems_in_cacheline;
return lda;
}
inline bool is_buffer_c_required(
dim_t acc_dt, dim_t dst_dt, bool with_sum) const {
const size_t k_chunk_elems = k_blk * batch_size;
if (nthr_k > 1 && static_cast<size_t>(mp.K) > k_chunk_elems)
return true;
return ((acc_dt != dst_dt || with_sum)
&& (static_cast<size_t>(mp.K) > k_chunk_elems
|| mp.K % k_blk > 0));
}
void update_configuration(brgemm_matmul_conf_t &bgmmc) const {
bgmmc.M_blk = m_blk;
bgmmc.M_chunk_size = m_chunks;
bgmmc.N_blk = n_blk;
bgmmc.N_chunk_size = n_chunks;
bgmmc.K_blk = rnd_up(k_blk, bgmmc.required_k_granularity);
bgmmc.brgemm_batch_size = batch_size;
bgmmc.nthr_k = nthr_k;
bgmmc.use_buffer_c = is_buffer_c_required(
bgmmc.acc_dt, bgmmc.dst_dt, bgmmc.with_sum);
bgmmc.LDA = bgmmc.adjust_a_strides || bgmmc.use_buffer_a
|| bgmmc.treat_A_as_plain
? get_actual_lda(bgmmc.use_buffer_a, bgmmc.tr_a_dt_sz)
: bgmmc.A_strides[1] / bgmmc.a_dt_sz;
}
};
float compute_blocking_heuristic_avx512(brgemm_matmul_conf_t &bgmmc,
const brgemm_matmul_conf_utils_t &bm_conf_utils,
const matmul_avx512_blocking_params_t::matmul_params_t &matmul,
matmul_avx512_blocking_params_t &best_blocking) {
const int nthr = bgmmc.nthr;
const int max_m_blk = nstl::min(256, matmul.M);
int min_m_blk = nstl::min(32, matmul.M);
dim_t min_m_chunks = div_up(matmul.M, max_m_blk);
int n_blk = bgmmc.N_blk;
const int n_chunks = div_up(matmul.N, n_blk);
const int max_n_chunks = bgmmc.use_buffer_a ? 16 : 1;
const int n_chunks_start = nstl::min(max_n_chunks, n_chunks);
// Note: do not extend K_blk for 'bwd_w' cases
const bool use_extended_k_blk = matmul.K > 1024
&& (!bm_conf_utils.check_is_transposed(bgmmc.src_tag));
int default_k_blk = use_extended_k_blk ? 1024 : 512;
int k_blk = nstl::min(matmul.K, default_k_blk);
int start_nthr_k = 1;
int last_nthr_k = 1;
// for cases with low parallel work, reduce 'min_m_blk' to
// increase potential parallelization balance.
const dim_t max_parallel = static_cast<dim_t>(matmul.batch) * n_chunks;
const dim_t max_bmn_parallel = max_parallel * min_m_chunks;
const bool low_parallel_work = nthr > max_parallel;
if (low_parallel_work) {
min_m_blk = nstl::min(matmul.M, 16);
// 2nd level tuning for low parallel work cases:
bool bwd_w_low_spatial_work
= bm_conf_utils.check_is_transposed(bgmmc.src_tag)
&& matmul.M <= 512;
bool low_spatial_work = matmul.M <= 40;
if (low_spatial_work || bwd_w_low_spatial_work) {
// Reduce n_blk size to increase parallel space
// note: over reduction of n_blk size on 2d shapes when n_chunks == 1
// showed significant performance degradation
if (!bm_conf_utils.check_n_blk_fixed()
&& IMPLICATION(n_chunks == 1, bgmmc.batch_ndims > 0))
n_blk = nstl::min(matmul.N, 32);
// force to plain B (wei) in small spatial size for FWD:
// note: this showed significant performance gain in WnD shapes
bool is_FWD = !(bm_conf_utils.check_is_transposed(bgmmc.wei_tag)
|| bm_conf_utils.check_is_transposed(bgmmc.src_tag));
if (bgmmc.use_buffer_b && is_FWD) {
bgmmc.use_buffer_b = bm_conf_utils.use_buffer_b(false);
}
}
// Parallelize across K for shapes with big 'K' dimension
bool bwd_w_par_k_blk = bgmmc.batch == 1
&& bm_conf_utils.check_is_transposed(bgmmc.src_tag)
&& !bm_conf_utils.is_int8()
&& IMPLICATION(bm_conf_utils.is_bf16(), math::is_pow2(matmul.K))
&& matmul.K >= 2048;
if (bwd_w_par_k_blk) {
start_nthr_k = nstl::min(nthr, 4);
assert(k_blk == nstl::min(matmul.K, 512));
}
// Enable k-partitioning for huge k and small m/n dimensions.
bool is_huge_k = matmul.K >= 20000;
bool is_small_mn = matmul.M <= 512 && matmul.N <= 512;
bool use_k_partitioning = is_huge_k && is_small_mn;
// TODO: expand to other data types.
use_k_partitioning = use_k_partitioning && bm_conf_utils.is_f32();
if (use_k_partitioning) {
auto least_prime_factor = [](int n) {
assert(n > 0);
if (n == 1) return 1;
for (int factor = 2; factor < n; factor++)
if (n % factor == 0) return factor;
return n;
};
int nthr_bmn = max_div(max_bmn_parallel, nthr);
int nthr_k = nstl::max(nthr / nthr_bmn, 1);
int nthr_remainder = nthr % nthr_bmn;
// Choose number of threads in k-dim to allow a larger block size
// for m-dim.
while (nthr_k <= nthr_remainder) {
nthr_bmn /= least_prime_factor(nthr_bmn);
nthr_k = nstl::max(nthr / nthr_bmn, 1);
nthr_remainder = nthr % nthr_bmn;
}
// Reduce number of threads in k-dim to balanced work.
dim_t k_chunks = div_up(matmul.K, k_blk);
while (k_chunks <= 5 * nthr_k && nthr_k > 1)
nthr_k /= least_prime_factor(nthr_k);
// Fix number of threads for k-dim.
start_nthr_k = nthr_k;
last_nthr_k = nthr_k;
}
}
// Use large m-blocking if possible.
const bool is_huge_n = matmul.N >= 20000;
const bool large_bmn_parallelism = max_bmn_parallel > 10 * nthr;
const bool has_m_tail = matmul.M % max_m_blk != 0;
const bool use_k_partitioning = start_nthr_k > 1;
bool use_large_m_blk = is_huge_n && large_bmn_parallelism && !has_m_tail;
use_large_m_blk &= !use_k_partitioning;
// TODO: Expand to other data types.
use_large_m_blk = use_large_m_blk && bm_conf_utils.is_f32();
if (use_large_m_blk) min_m_blk = max_m_blk;
matmul_avx512_blocking_params_t cur_params(matmul, nthr);
float best_imbalance = 1.f; // reduce
for (int nthr_k = start_nthr_k; nthr_k >= last_nthr_k; --nthr_k) {
bool found_best_blocking = false;
for_(int n_chunk_size = n_chunks_start; n_chunk_size >= 1;
--n_chunk_size)
for (int m_blk = max_m_blk; m_blk >= min_m_blk; --m_blk) {
cur_params.update_params(
1, m_blk, n_chunk_size, n_blk, 1, k_blk, nthr_k);
float cur_imbalance = cur_params.get_imbalance();
const int m_chunk_size = 1;
int m_chunks = div_up(bgmmc.M, m_blk * m_chunk_size);
int n_chunks = div_up(bgmmc.N, n_blk * n_chunk_size);
int work_amount = bgmmc.batch * m_chunks * n_chunks;
int nthr_bmn = nthr / nthr_k;
bool skip_config = work_amount < nthr_bmn * 3
&& work_amount % nthr_bmn != 0 && start_nthr_k == 1;
if (skip_config) continue;
if (cur_imbalance < best_imbalance) {
best_imbalance = cur_imbalance;
best_blocking = cur_params;
found_best_blocking = true;
}
}
if (!found_best_blocking) {
cur_params.update_params(1, min_m_blk, 1, n_blk, 1, k_blk, nthr_k);
float cur_imbalance = cur_params.get_imbalance();
if (cur_imbalance < best_imbalance) {
best_imbalance = cur_imbalance;
best_blocking = cur_params;
}
}
}
return best_imbalance;
}
float compute_blocking_heuristic_avx2(brgemm_matmul_conf_t &bgmmc,
const brgemm_matmul_conf_utils_t &bm_conf_utils,
const matmul_avx512_blocking_params_t::matmul_params_t &matmul,
matmul_avx512_blocking_params_t &best_blocking) {
const int nthr = bgmmc.nthr;
const int max_m_blk = nstl::min(/*64*/ 256, matmul.M);
int min_m_blk = nstl::min(32, matmul.M); // max_m_blk
int n_blk = bgmmc.N_blk;
const int n_chunks = div_up(matmul.N, n_blk);
const int max_n_chunks = bgmmc.use_buffer_a ? 16 : 1;
const int n_chunks_start = nstl::min(max_n_chunks, n_chunks);
int default_k_blk = 1024;
int k_blk = nstl::min(matmul.K, default_k_blk);
int start_nthr_k = 1;
// for cases with low parallel work, reduce 'min_m_blk' to
// increase potential parallelization balance.
const size_t max_parallel = matmul.batch * n_chunks;
const bool low_parallel_work = static_cast<size_t>(nthr) > max_parallel;
if (low_parallel_work) {
min_m_blk = nstl::min(matmul.M, 16);
bool low_spatial_work = matmul.M <= 40;
if (low_spatial_work) {
// Reduce n_blk size to increase parallel space
// note: over reduction of n_blk size on 2d shapes when n_chunks == 1
// showed significant performance degradation
if (!bm_conf_utils.check_n_blk_fixed()
&& IMPLICATION(n_chunks == 1, bgmmc.batch_ndims > 0))
n_blk = nstl::min(matmul.N, 32);
}
}
float best_imbalance = 1.f; // reduce
for_(int nthr_k = start_nthr_k; nthr_k >= 1; --nthr_k)
for_(int n_chunk_size = n_chunks_start; n_chunk_size >= 1; --n_chunk_size)
for (int m_blk = max_m_blk; m_blk >= min_m_blk; --m_blk) {
matmul_avx512_blocking_params_t cur_params(matmul, nthr);
cur_params.update_params(
1, m_blk, n_chunk_size, n_blk, 1, k_blk, nthr_k);
float cur_imbalance = cur_params.get_imbalance();
if (cur_imbalance < best_imbalance) {
best_imbalance = cur_imbalance;
best_blocking = cur_params;
}
}
return best_imbalance;
}
float compute_blocking_heuristic_avx2_f32(brgemm_matmul_conf_t &bgmmc,
const brgemm_matmul_conf_utils_t &bm_conf_utils,
const matmul_avx512_blocking_params_t::matmul_params_t &matmul,
matmul_avx512_blocking_params_t &best_blocking) {
float best_imbalance = 1.f; // reduce
const int nthr = bgmmc.nthr;
dim_t max_m_blk = nstl::min(256, matmul.M);
dim_t min_m_blk = max_m_blk;
int n_blk = bgmmc.N_blk;
const int n_chunks = div_up(matmul.N, n_blk);
const int max_n_chunks = bgmmc.use_buffer_a ? 16 : 1;
const int n_chunks_start = nstl::min(max_n_chunks, n_chunks);
int default_k_blk = 1024;
int k_blk = nstl::min(matmul.K, default_k_blk);
int start_nthr_k = 1;
// for cases with low parallel work, reduce 'min_m_blk' to
// increase potential parallelization balance.
size_t max_parallel = matmul.batch * n_chunks;
const float req_additional_parallel = nthr / max_parallel;
if (req_additional_parallel > 1) {
min_m_blk = saturate<int>(
16, max_m_blk, matmul.M / req_additional_parallel);
max_parallel *= div_up(matmul.M, min_m_blk);
} else if (bm_conf_utils.check_is_transposed(bgmmc.src_tag)
&& matmul.K >= 4096) {
min_m_blk = nstl::max(16, matmul.M / 4);
default_k_blk = 192;
}
bool low_parallel_work = max_parallel % nthr != 0
&& (static_cast<float>(max_parallel) / nthr) < 2;
if (low_parallel_work) {
// Reduce n_blk size to increase parallel space
// note: over reduction of n_blk size on 2d shapes when n_chunks == 1
// showed significant performance degradation
if (!bm_conf_utils.check_n_blk_fixed()
&& IMPLICATION(n_chunks == 1, bgmmc.batch_ndims > 0)) {
n_blk = nstl::min(matmul.N, 16);
}
}
max_m_blk = nstl::max(max_m_blk, min_m_blk);
for_(int nthr_k = start_nthr_k; nthr_k >= 1; --nthr_k)
for_(int n_chunk_size = n_chunks_start; n_chunk_size >= 1; --n_chunk_size)
for (int m_blk = min_m_blk; m_blk <= max_m_blk; m_blk += 4) {
matmul_avx512_blocking_params_t cur_params(matmul, nthr);
cur_params.update_params(
1, m_blk, n_chunk_size, n_blk, 1, k_blk, nthr_k);
float cur_imbalance = cur_params.get_imbalance();
if (cur_imbalance < best_imbalance) {
best_imbalance = cur_imbalance;
best_blocking = cur_params;
}
}
return best_imbalance;
}
status_t compute_blocking_heuristic(brgemm_matmul_conf_t &bgmmc,
const brgemm_matmul_conf_utils_t &bm_conf_utils) {
bgmmc.N_blk = bgmmc.wei_n_blk;
if (!bgmmc.is_runtime_N) bgmmc.N_blk = nstl::min(bgmmc.N_blk, bgmmc.N);
bgmmc.M_chunk_size = bgmmc.N_chunk_size = bgmmc.K_chunk_size = 1;
bool prefer_copy_a
= one_of(true, bm_conf_utils.is_f32() && bgmmc.isa == avx2,
bm_conf_utils.is_bf16(),
bm_conf_utils.is_bf16_with_int_wei(),
(bgmmc.is_amx
&& (bm_conf_utils.is_f16()
|| bm_conf_utils.is_f16_with_int_wei())))
&& (bgmmc.isa != avx2_vnni_2) // no perf study yet.
&& bgmmc.lda_big_pow2() && bgmmc.M >= 1024;
// Avoid copying A for small N gives better performance.
// TODO: Expand for other precisions and cases.
if (bgmmc.is_amx && bm_conf_utils.is_int8())
prefer_copy_a &= bgmmc.N >= 256;
if (bgmmc.is_amx) {
if (matmul_amx_blocking_params_macro_t::is_supported(
bgmmc, bm_conf_utils)) {
//grid heuristic is possible best blocking is set
matmul_amx_blocking_params_macro_t best_blocking(bgmmc);
matmul_amx_blocking_params_macro_t::find_best_blocking(
bgmmc, bm_conf_utils, best_blocking);
if (best_blocking.get_blocking_scores() != 0.0f) {
best_blocking.update_configuration(bgmmc);
return status::success;
}
}
bgmmc.use_buffer_a |= prefer_copy_a;
// Configure matrix sizes
if (bgmmc.is_runtime_M) {
bgmmc.M_blk = 64; // use fixed block size for runtime M case
} else {
auto get_block_candidate = [&]() -> dim_t {
// for AMX prefer block sizes which utilize at least 13 tile
// rows
const dim_t tile_rows_min = 13;