-
Notifications
You must be signed in to change notification settings - Fork 1k
/
Copy pathzp_plan.cpp
1668 lines (1473 loc) · 58.8 KB
/
zp_plan.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*******************************************************************************
* Copyright 2023-2025 Intel Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "gpu/intel/jit/conv/zp_plan.hpp"
#include "common/utils.hpp"
#include "gpu/intel/jit/conv/config.hpp"
#include "gpu/intel/jit/conv/plan_utils.hpp"
#include "gpu/intel/jit/ir/fma.hpp"
#include "gpu/intel/jit/ir/gemm_schedule.hpp"
#include "gpu/intel/jit/ir/message.hpp"
#include "gpu/intel/jit/ir/send_plan.hpp"
#include "gpu/intel/jit/ir/tensor.hpp"
#include "gpu/intel/jit/utils/utils.hpp"
namespace dnnl {
namespace impl {
namespace gpu {
namespace intel {
namespace jit {
enum class zp_comp_kind_t {
undef,
// z:s32, w:x8, c:s32
// c = 0
// dp4a(c, c, w, 0x01010101)
// mul (c, c, z)
wei_Xn4k_x8_zp_common,
// z:s32, w:x8, c:s32
// c = 0
// mad(c, c, z, w_s16) 4x for 4i reduction
wei_Xn4k_x8_zp_per_k,
// z:s32, w:s16, c:s32
// c = 0
// mad(c, c, z, w)
wei_Xb_s16,
// z:s32, w:s16, c:s32
// c = 0
// mad(c, c, z, w)
wei_Xn_s16,
};
inline std::string to_string(zp_comp_kind_t kind) {
switch (kind) {
#define CASE(name) \
case zp_comp_kind_t::name: return #name
CASE(undef);
CASE(wei_Xn4k_x8_zp_common);
CASE(wei_Xn4k_x8_zp_per_k);
CASE(wei_Xb_s16);
CASE(wei_Xn_s16);
default: gpu_error_not_expected();
#undef CASE
}
return "unknown";
}
inline std::ostream &operator<<(std::ostream &out, zp_comp_kind_t kind) {
out << to_string(kind);
return out;
}
static bool ends_with(
const layout_t &layout, dim_idx_t i0, int b0, bool strict = false) {
if (layout.nblocks() < 1) return false;
auto &blocks = layout.blocks();
if (blocks[0].dim_idx != i0) return false;
if (strict && blocks[0].block != b0) return false;
if (!strict && blocks[0].block % b0 != 0) return false;
return true;
}
static bool ends_with(
const layout_t &layout, dim_idx_t i1, int b1, int i0, int b0) {
if (!ends_with(layout, i0, b0, /*strict=*/true)) return false;
if (layout.nblocks() < 2) return false;
auto &blocks = layout.blocks();
if (blocks[1].dim_idx != i1) return false;
if (blocks[1].block % b1 != 0) return false;
return true;
}
static type_t dpas_type(type_t t) {
return (t.is_int()) ? (t.is_signed()) ? type_t::s32() : type_t::u32() : t;
}
static void get_kw_ic_from_b_view(const gemm_schedule_t &gemm_schedule,
expr_t &kw_var, expr_t &ic_var, dim_t &kw, dim_t &ic) {
loop_kind_t exp_loops = loop_kind_t::tg_grid | loop_kind_t::kernel_grid
| loop_kind_t::serial;
auto &view = gemm_schedule.b_view();
auto ic_var_tmp = view.vvar("ic");
ic = view.vdims()[view.vvar_index(ic_var_tmp)];
ic_var = gemm_schedule.expand(ic_var_tmp, true, exp_loops);
auto kw_var_tmp = view.vvar("kw");
kw = view.vdims()[view.vvar_index(kw_var_tmp)];
kw_var = gemm_schedule.expand(kw_var_tmp, true, exp_loops);
}
class split_dispatcher_t {
public:
split_dispatcher_t() = default;
split_dispatcher_t(const layout_t &comp_layout, const layout_t &c_layout,
const hw_t &hw, bool is_fwd, const bmnk_mapper_t &mapper) {
gpu_assert(comp_layout.ndims() == 6);
comp_g_idx_ = 0;
comp_c_idx_ = (is_fwd) ? 1 : 2;
c_g_idx_ = 1;
c_c_idx_ = 2;
for (auto abc : {abc_kind_t::a, abc_kind_t::b}) {
for (int factor : {2, 4}) {
auto &splits = (abc == abc_kind_t::a) ? a_splits_ : b_splits_;
if ((int)splits.size() <= factor) splits.resize(factor + 1);
splits[factor] = split_t(
c_layout, mapper, abc, factor, simd_dim_idx_, simd_);
}
}
for (int b : {32, 16, 8}) {
if (b > 16 && hw < ngen::HW::XeHPC) continue;
if (ends_with(comp_layout, comp_g_idx_, b)
&& ends_with(c_layout, c_g_idx_, b)) {
simd_dim_idx_ = 1;
simd_ = b;
simd_tile_ = get_simd_tile(c_layout);
return;
}
if (ends_with(comp_layout, comp_c_idx_, b)
&& ends_with(c_layout, c_c_idx_, b)) {
simd_dim_idx_ = 2;
simd_ = b;
simd_tile_ = get_simd_tile(c_layout);
return;
}
}
gpu_error_not_expected()
<< "Can't initialize SIMD size, comp_layout = " << comp_layout
<< ", c_layout = " << c_layout;
}
int simd() const { return simd_; }
std::string simd_str() const {
auto di_str = std::to_string(simd_dim_idx_);
return std::to_string(simd_) + " (dim_idx: " + di_str + ")";
}
const tensor_t &get_simd_tile() const { return simd_tile_; }
std::vector<dim_t> c_to_comp(const std::vector<dim_t> &c) const {
// c: ngcdhw or ngc[osp]
// comp: goidhw
std::vector<dim_t> ret(6);
ret[comp_g_idx_] = c[c_g_idx_];
ret[comp_c_idx_] = c[c_c_idx_];
return ret;
}
bool can_split(abc_kind_t abc, int factor) const {
if (factor == 1) return true;
auto &splits = (abc == abc_kind_t::a) ? a_splits_ : b_splits_;
if (factor >= (int)splits.size()) return false;
return (bool)splits[factor];
}
void set_split(abc_kind_t abc, int factor) {
gpu_assert(can_split(abc, factor));
if (factor == 1) {
split_ = split_t::no_split();
return;
}
auto &splits = (abc == abc_kind_t::a) ? a_splits_ : b_splits_;
split_ = splits[factor];
}
abc_kind_t abc() const { return split_.abc(); }
int factor() const { return split_.factor(); }
explicit operator bool() const { return bool(split_); }
bool in_subtile(const std::vector<dim_t> &start, int subtile_idx) const {
return split_.in_subtile(start, subtile_idx);
}
private:
class split_t {
public:
split_t() = default;
split_t(const layout_t &c, const bmnk_mapper_t &mapper, abc_kind_t abc,
int factor, dim_idx_t simd_dim_idx, int simd) {
gpu_assert(factor > 1);
bmnk_kind_t split_mn
= (abc == abc_kind_t::a ? bmnk_kind_t::m : bmnk_kind_t::n);
dim_t dim = 1;
std::vector<block_t> mn_blocks;
for (auto &b : c.blocks()) {
if (b.block == 1) continue;
auto bmnk = mapper.bmnk_kind(abc_kind_t::c, b.dim_idx);
if (bmnk != split_mn) continue;
dim *= b.block;
mn_blocks.push_back(b);
}
if (dim % factor != 0) return;
dim_t subtile_dim = dim / factor;
dim_t cur_dim = 1;
dim_idx_t cur_idx = dim_idx::invalid;
for (auto &b : mn_blocks) {
if (cur_idx == dim_idx::invalid) {
cur_idx = b.dim_idx;
} else if (b.dim_idx != cur_idx) {
return;
}
dim_t max_block = std::min(b.block, subtile_dim / cur_dim);
if (b.block % max_block != 0) return;
cur_dim *= max_block;
if (cur_dim == subtile_dim) break;
}
if (cur_dim != subtile_dim) return;
if (cur_idx == simd_dim_idx && cur_dim < simd) return;
abc_ = abc;
factor_ = factor;
dim_idx_ = cur_idx;
subtile_dim_ = subtile_dim;
}
static split_t no_split() {
split_t ret;
ret.factor_ = 1;
return ret;
}
abc_kind_t abc() const { return abc_; }
int factor() const { return factor_; }
explicit operator bool() const { return factor_ != 0; }
bool in_subtile(
const std::vector<dim_t> &start, int subtile_idx) const {
if (!*this) return false;
if (factor_ == 1) return true;
dim_t beg = subtile_idx * subtile_dim_;
dim_t end = beg + subtile_dim_;
return start[dim_idx_] >= beg && start[dim_idx_] < end;
}
private:
abc_kind_t abc_ = abc_kind_t::undef;
int factor_ = 0;
dim_idx_t dim_idx_ = dim_idx::invalid;
dim_t subtile_dim_ = -1;
};
tensor_t get_simd_tile(const layout_t &c_layout) const {
std::vector<dim_t> tile_dims(c_layout.ndims(), 1);
tile_dims[simd_dim_idx_] = simd_;
return tensor_t(tile_dims);
}
int comp_g_idx_ = -1;
int comp_c_idx_ = -1;
int c_g_idx_ = -1;
int c_c_idx_ = -1;
int simd_dim_idx_ = -1; // C layout index.
int simd_ = -1;
std::vector<split_t> a_splits_;
std::vector<split_t> b_splits_;
split_t split_ = split_t::no_split();
tensor_t simd_tile_;
};
class zp_wei_init_plan_t : public base_plan_t {
public:
using base_plan_t::base_plan_t;
operator bool() const { return simd_ != -1; }
zp_wei_init_plan_t(const hw_t &hw, bool is_fwd, int simd, type_t data_type,
const layout_t &zp_layout, const layout_t &b_layout)
: base_plan_t(hw)
, zp_layout_(zp_layout)
, b_layout_(b_layout)
, data_type_(data_type)
, simd_(simd) {
gpu_assert(zp_layout_.blocks().empty());
}
int wei_reg_buf_size() const {
gpu_assert(b_layout_.size()
% (sdepth_ * simd_ * dpas_type(data_type_).size())
== 0);
return utils::rnd_up(into<int>(b_layout_.size()), grf_size());
}
int estimate_regs() const {
return utils::div_up(wei_reg_buf_size(), grf_size());
}
stmt_t create_stmt(const expr_t &wei_buf, const expr_t &dpas_buf,
const gemm_schedule_t &gemm_schedule, int subtile_idx) {
if (subtile_idx > 0) return stmt_t();
gpu_assert(zp_layout_.blocks().empty());
auto data_size = data_type_.size();
auto dpas_size = dpas_type(data_type_).size();
auto sdepth_size = simd_ * dpas_size;
gpu_assert(zp_layout_.type().is_s8());
auto wei_load = -load_t::make(zp_layout_.type(), wei_buf, 0);
stmt_t stmt = store_t::make(wei_buf, 0, wei_load);
int size = dpas_size / data_size;
if (size > 1) {
wei_load = shuffle_t::make_broadcast(
load_t::make(data_type_, wei_buf, 0), size);
stmt = stmt.append(store_t::make(dpas_buf, 0,
cast_t::make(data_type_.with_elems(size), wei_load)));
}
expr_t kw_var, ic_var;
dim_t kw = 0, ic = 0;
get_kw_ic_from_b_view(gemm_schedule, kw_var, ic_var, kw, ic);
kw_var = simd_bcast(kw_var);
bool small_ic = is_small(data_type_, ic);
dim_idx_t kw_idx = 5; // TODO: support non-forward kw!
std::vector<dim_t> tile_dim(b_layout_.ndims(), 1);
for (auto &b : b_layout_.blocks()) {
if (b.dim_idx == kw_idx) break;
tile_dim[b.dim_idx] *= b.block;
}
tensor_t tile(tile_dim);
gpu_assert(tile.elems() % sdepth_size == 0);
wei_load = simd_bcast(load_t::make(
dpas_type(data_type_), (size > 1) ? dpas_buf : wei_buf, 0));
b_layout_.for_each_tile(tile, [&](const std::vector<dim_t> &start) {
auto off = b_layout_.offset_in_bytes(start);
auto mask = (small_ic) ? kw_var < simd_bcast(kw - start[kw_idx])
: expr_t();
for (int i = 0; i < tile.elems(); i += sdepth_size)
stmt = stmt.append(store_t::make(dpas_buf, off + i, wei_load,
store_t::default_stride, mask, true));
});
return stmt;
}
std::string str() const {
std::ostringstream oss;
oss << "zp_wei_layout: " << zp_layout_ << std::endl;
oss << "b_layout: " << b_layout_ << std::endl;
oss << "data_type: " << data_type_ << std::endl;
oss << "dpas_type: " << dpas_type(data_type_) << std::endl;
oss << "sdepth: " << sdepth_ << std::endl;
oss << "SIMD: " << simd_;
return add_indent("wei_init", oss.str());
}
IR_DEFINE_DUMP()
private:
expr_t simd_bcast(const expr_t &e) const {
return shuffle_t::make_broadcast(e, simd_);
}
layout_t zp_layout_;
layout_t b_layout_;
type_t data_type_;
int sdepth_ = 8;
int simd_ = -1;
};
class zp_comp_init_plan_t : public base_plan_t {
public:
using base_plan_t::base_plan_t;
zp_comp_init_plan_t(const hw_t &hw, bool is_fwd, const layout_t &zp_layout,
const layout_t &src_layout, const layout_t &wei_layout)
: base_plan_t(hw)
, zp_layout_(zp_layout)
, src_layout_(src_layout)
, wei_layout_(wei_layout) {
init_idxs(is_fwd);
init_comp_layout();
init_comp_kind();
}
const layout_t &zp_layout() const { return zp_layout_; }
const layout_t &src_layout() const { return src_layout_; }
const layout_t &comp_layout() const { return comp_layout_; }
int ndims() const { return comp_layout_.ndims(); }
int fill_reg_buf_size() const {
return utils::rnd_up(into<int>(src_layout_.size()), grf_size());
}
int comp_reg_buf_size() const {
int ret = utils::div_up(into<int>(comp_layout_.size()), split_factor_);
ret = utils::rnd_up(ret, grf_size());
return ret;
}
bool can_split(abc_kind_t abc, int factor) const {
if (abc != abc_kind_t::b || factor == 1) return true;
if (wei_layout_.is_empty()) return false;
if (comp_layout_.is_empty()) return false;
auto &b_wei = wei_layout_.blocks().back();
auto &b_comp = comp_layout_.blocks().back();
if (b_wei.block % factor != 0) return false;
if (b_wei.block != b_comp.block) return false;
if (b_wei.dim_idx != b_comp.dim_idx) return false;
int dim_idx = b_comp.dim_idx;
dim_t subtile_dim = comp_layout_.dim(dim_idx);
if (dim_idx == simd_dim_idx_ && subtile_dim < simd_) return false;
return true;
}
void set_split(abc_kind_t abc, int factor) {
gpu_assert(can_split(abc, factor));
if (abc == abc_kind_t::b) split_factor_ = factor;
}
int estimate_fill_regs() const {
return utils::div_up(fill_reg_buf_size(), grf_size());
}
int estimate_regs() const {
int ret = comp_reg_buf_size();
switch (kind_) {
case zp_comp_kind_t::wei_Xn4k_x8_zp_common:
// zp_1x4 buffer.
ret += grf_size();
break;
case zp_comp_kind_t::wei_Xn4k_x8_zp_per_k:
// wei_s16 buffer.
ret += utils::rnd_up(simd_ * 4, grf_size());
break;
default: break;
}
return utils::div_up(ret, grf_size());
}
stmt_t create_fill_stmt(
const expr_t &src_buf, const expr_t &dpas_buf) const {
auto int8_bcast4 = [](const expr_t &buf) {
auto load = load_t::make(type_t::u8(), buf, 0);
return store_t::make(buf, 0,
cast_t::make(
type_t::u8(4), shuffle_t::make_broadcast(load, 4)));
};
auto stmt = int8_bcast4(src_buf);
stmt = stmt.append(store_t::make(
dpas_buf, 0, -load_t::make(type_t::s8(), src_buf, 0)));
stmt = stmt.append(int8_bcast4(dpas_buf));
auto fill = simd_bcast(load_t::make(type_t::u32(), dpas_buf, 0));
for (int i = 0; i < src_layout_.size(); i += simd_ * 4)
stmt = stmt.append(store_t::make(dpas_buf, i, fill));
return stmt;
}
stmt_t create_stmt(buffer_manager_t &buf_mgr, const expr_t &zp_buf,
const expr_t &wei_buf, const expr_t &comp_buf,
const expr_t &src_buf, const gemm_schedule_t &gemm_schedule,
int subtile_idx) const {
if (split_factor_ == 1 && subtile_idx > 0) return stmt_t();
stmt_t stmt, comp_buf_fill;
int ck_blk = 1;
switch (kind_) {
case zp_comp_kind_t::wei_Xn4k_x8_zp_common:
case zp_comp_kind_t::wei_Xn4k_x8_zp_per_k: ck_blk = 4; break;
default: break;
}
expr_t kw_var, ic_var;
dim_t kw = 0, ic = 0;
get_kw_ic_from_b_view(gemm_schedule, kw_var, ic_var, kw, ic);
kw_var = simd_bcast(kw_var);
bool small_ic = is_small(wei_layout_.type(), ic);
int kw_idx = 5; // TODO: support non-forward kw!
auto load_mul = binary_op_t::make(op_kind_t::_max,
binary_op_t::make(op_kind_t::_min,
simd_bcast(-ic_var) + simd_bcast(ic),
simd_bcast(wei_layout_.dim(ck_idx_))),
simd_bcast(0));
auto load_wei = simd_bcast(load_t::make(
type_t::s16(), (src_buf.is_empty()) ? comp_buf : src_buf, 0));
comp_layout_.for_each_tile(
get_simd_tile(), [&](const std::vector<dim_t> &start) {
if (!in_subtile(start, subtile_idx)) return;
auto comp = comp_buf[get_comp_off(start)];
for (int ck = 0; ck < wei_layout_.dim(ck_idx_);
ck += ck_blk) {
auto zp = zp_buf[get_zp_off(start, ck)];
auto wei = wei_buf[get_wei_off(start, ck)];
stmt = stmt.append(
create_tile_stmt(zp, wei, comp, buf_mgr));
}
stmt = stmt.append(create_zp_common_mul_stmt(zp_buf, comp));
// TODO: this implies that zp_wei and zp_src are scalar
auto mask = kw_var < simd_bcast(kw - start[kw_idx]);
mask = (!src_buf.is_empty())
? (small_ic) ? mask : simd_bcast(expr_t(bool(true)))
: simd_bcast(expr_t(bool(false)));
comp_buf_fill = comp_buf_fill.append(
store_t::make(comp, 0, load_mul * load_wei,
store_t::default_stride, mask, true));
});
auto zp_1x4 = buf_mgr.get("zp_1x4");
if (!zp_1x4.is_empty()) {
if (zp_layout_.type().is_s8()) {
auto load = load_t::make(
zp_layout_.type(), buf_mgr.get("zp_src"), 0);
auto init = store_t::make(zp_1x4, 0,
cast_t::make(type_t::u8(4),
shuffle_t::make_broadcast(load, 4)));
stmt = init.append(stmt);
} else {
auto init = store_t::make(zp_1x4, 0, 0x01010101);
stmt = init.append(stmt);
}
}
return comp_buf_fill.append(stmt);
}
std::string str() const {
std::ostringstream oss;
oss << "zp_layout: " << zp_layout_ << std::endl;
oss << "src_layout: " << src_layout_ << std::endl;
oss << "wei_layout: " << wei_layout_ << std::endl;
oss << "comp_layout: " << comp_layout_ << std::endl;
oss << "kind: " << kind_ << std::endl;
oss << "SIMD: " << simd_;
return add_indent("comp_init", oss.str());
}
IR_DEFINE_DUMP()
private:
expr_t simd_bcast(const expr_t &e) const {
return shuffle_t::make_broadcast(e, simd_);
}
void init_idxs(bool is_fwd) {
g_idx_ = 0;
cn_idx_ = is_fwd ? 1 : 2;
ck_idx_ = is_fwd ? 2 : 1;
}
void init_comp_layout() {
auto blocks = wei_layout_.blocks();
for (auto &b : blocks) {
if (b.dim_idx == ck_idx_) b.block = 1;
}
comp_layout_ = layout_t(type_t::s32(), wei_layout_.ndims(), 0, blocks);
comp_layout_ = comp_layout_.make_dense();
}
void init_comp_kind() {
if (is_wei_Xn4k_x8_zp_common(simd_dim_idx_, simd_)) {
kind_ = zp_comp_kind_t::wei_Xn4k_x8_zp_common;
} else if (is_wei_Xn4k_x8_zp_per_k(simd_dim_idx_, simd_)) {
kind_ = zp_comp_kind_t::wei_Xn4k_x8_zp_per_k;
} else if (is_wei_Xb_s16(simd_dim_idx_, simd_)) {
kind_ = zp_comp_kind_t::wei_Xb_s16;
} else if (is_wei_Xn_s16(simd_dim_idx_, simd_)) {
kind_ = zp_comp_kind_t::wei_Xn_s16;
} else {
gpu_error_not_expected() << wei_layout_;
}
}
bool is_zp_common() const { return zp_layout_.elems() == 1; }
bool is_wei_Xn4k_x8_zp_common(int &vec_dim_idx, int &simd) const {
if (!wei_layout_.type().is_x8()) return false;
if (!is_zp_common()) return false;
for (int cn_blk : {16, 8}) {
if (ends_with(wei_layout_, cn_idx_, cn_blk, ck_idx_, 4)) {
vec_dim_idx = cn_idx_;
simd = cn_blk;
return true;
}
}
return false;
}
bool is_wei_Xn4k_x8_zp_per_k(int &vec_dim_idx, int &simd) const {
if (!wei_layout_.type().is_x8()) return false;
if (is_zp_common()) return false;
for (int cn_blk : {16, 8}) {
if (ends_with(wei_layout_, cn_idx_, cn_blk, ck_idx_, 4)) {
vec_dim_idx = cn_idx_;
simd = cn_blk;
return true;
}
}
return false;
}
bool is_wei_Xy_s16(int y_idx, int &vec_dim_idx, int &simd) const {
for (int y_blk : {32, 16, 8}) {
if (y_blk > 16 && hw < ngen::HW::XeHPC) continue;
if (ends_with(wei_layout_, y_idx, y_blk)) {
vec_dim_idx = y_idx;
simd = y_blk;
return true;
}
}
return false;
}
bool is_wei_Xb_s16(int &vec_dim_idx, int &simd) const {
return is_wei_Xy_s16(g_idx_, vec_dim_idx, simd);
}
bool is_wei_Xn_s16(int &vec_dim_idx, int &simd) const {
return is_wei_Xy_s16(cn_idx_, vec_dim_idx, simd);
}
tensor_t get_simd_tile() const {
std::vector<dim_t> tile_dims(ndims(), 1);
tile_dims[simd_dim_idx_] = simd_;
return tensor_t(tile_dims);
}
int get_comp_off(const std::vector<dim_t> &start) const {
int off = (int)comp_layout_.offset_in_bytes(start);
return off % comp_reg_buf_size();
}
int wei_reg_buf_size() const {
int ret = utils::div_up(into<int>(wei_layout_.size()), split_factor_);
ret = utils::rnd_up(ret, grf_size());
return ret;
}
int get_wei_off(const std::vector<dim_t> &_start, int ck) const {
auto start = _start;
start[ck_idx_] = ck;
int off = (int)wei_layout_.offset_in_bytes(start);
return off % wei_reg_buf_size();
}
int get_zp_off(const std::vector<dim_t> &_start, int ck) const {
std::vector<dim_t> start(2);
start[0] = _start[g_idx_];
start[1] = is_zp_common() ? 0 : ck;
int off = (int)zp_layout_.offset_in_bytes(start);
return off;
}
bool in_subtile(const std::vector<dim_t> &start, int subtile_idx) const {
if (split_factor_ == 1) return true;
auto &b = comp_layout_.blocks().back();
dim_t subtile_dim = ir_utils::safe_divide(
comp_layout_.dim(b.dim_idx), split_factor_);
dim_t beg = subtile_idx * subtile_dim;
dim_t end = beg + subtile_dim;
return start[b.dim_idx] >= beg && start[b.dim_idx] < end;
}
stmt_t create_tile_stmt(const expr_t &zp, const expr_t &wei,
const expr_t &comp, buffer_manager_t &buf_mgr) const {
switch (kind_) {
case zp_comp_kind_t::wei_Xn4k_x8_zp_common:
return create_tile_wei_Xn4k_x8_zp_common(
zp, wei, comp, buf_mgr);
case zp_comp_kind_t::wei_Xn4k_x8_zp_per_k:
return create_tile_wei_Xn4k_x8_zp_per_k(zp, wei, comp, buf_mgr);
case zp_comp_kind_t::wei_Xb_s16:
case zp_comp_kind_t::wei_Xn_s16:
return create_tile_wei_Xy_s16(zp, wei, comp, buf_mgr);
default: gpu_error_not_expected();
}
return stmt_t();
}
stmt_t create_zp_common_mul_stmt(
const expr_t &zp, const expr_t &comp) const {
auto zp_type = zp_layout_.type();
if ((kind_ != zp_comp_kind_t::wei_Xn4k_x8_zp_common) || zp_type.is_s8())
return stmt_t();
auto comp_type = comp_layout_.type();
auto comp_load = load_t::make(comp_type.with_elems(simd_), comp, 0);
auto zp_load = load_t::make(zp_type, zp, 0);
auto zp_bcast = shuffle_t::make_broadcast(zp_load, simd_);
auto comp_store = store_t::make(comp, 0, comp_load * zp_bcast);
return comp_store;
}
stmt_t create_tile_wei_Xn4k_x8_zp_common(const expr_t &zp,
const expr_t &wei, const expr_t &comp,
buffer_manager_t &buf_mgr) const {
UNUSED(zp);
auto comp_type = comp_layout_.type();
auto wei_type
= wei_layout_.type().is_s8() ? type_t::s32() : type_t::u32();
auto _1x4_type = type_t::s32();
auto dp4a = dpas_t::make_dp4a(simd_, comp_type, wei_type, _1x4_type);
auto zp_1x4 = buf_mgr.get("zp_1x4", grf_size());
return dp4a.call({comp, comp, wei, std::move(zp_1x4)});
}
stmt_t create_tile_wei_Xn4k_x8_zp_per_k(const expr_t &zp, const expr_t &wei,
const expr_t &comp, buffer_manager_t &buf_mgr) const {
int zp_stride = 0;
int wei_s16_stride = 2;
auto zp_type = zp_layout_.type();
auto wei_x8_type = wei_layout_.type();
auto wei_s16_type = type_t::s16();
auto comp_type = comp_layout_.type();
auto real_zp = zp;
auto wei_s16_buf = buf_mgr.get(
"zp_wei_s16", simd_ * wei_s16_type.size() * wei_s16_stride);
auto ret = maybe_typecast_zp_src(buf_mgr, zp_type, real_zp, 4);
auto mad = mad_t::make(hw, comp_type, simd_, zp_type, zp_stride,
wei_s16_type, wei_s16_stride);
for (int ic = 0; ic < 4; ic++) {
auto wei_x8
= load_t::make(wei_x8_type.with_elems(simd_), wei, ic, 4);
auto wei_s16 = cast(wei_x8, wei_s16_type.with_elems(simd_));
auto store_s16 = store_t::make(wei_s16_buf, 0, wei_s16,
wei_s16_stride * type_t::s16().size());
ret = ret.append(store_s16);
ret = ret.append(mad.call(
{comp, comp, real_zp + zp_type.size() * ic, wei_s16_buf}));
}
return ret;
}
stmt_t create_tile_wei_Xy_s16(const expr_t &zp, const expr_t &wei,
const expr_t &comp, buffer_manager_t &buf_mgr) const {
int zp_stride = (kind_ == zp_comp_kind_t::wei_Xb_s16 && !is_zp_common())
? 1
: 0;
int wei_stride = 2;
auto zp_type = zp_layout_.type();
auto wei_type = wei_layout_.type();
auto comp_type = comp_layout_.type();
auto real_zp = zp;
gpu_assert((int)comp_layout_.inner_stride() == 1);
gpu_assert(wei_type.is_s16());
gpu_assert((int)wei_layout_.inner_stride() == wei_stride);
auto ret = maybe_typecast_zp_src(
buf_mgr, zp_type, real_zp, (zp_stride) ? simd_ : 1);
auto mad = mad_t::make(
hw, comp_type, simd_, zp_type, zp_stride, wei_type, wei_stride);
return ret.append(mad.call({comp, comp, std::move(real_zp), wei}));
}
stmt_t maybe_typecast_zp_src(buffer_manager_t &buf_mgr, type_t &type,
expr_t &zp, int size) const {
auto real_type = type_t::s32();
stmt_t ret;
if (type != real_type) {
auto src_zp = load_t::make(type.with_elems(size), zp, 0);
zp = buf_mgr.get("zp_src_s32", real_type.size() * size);
ret = store_t::make(
zp, 0, cast(src_zp, real_type.with_elems(size)));
type = real_type;
}
return ret;
}
dim_idx_t g_idx_ = -1;
dim_idx_t cn_idx_ = -1;
dim_idx_t ck_idx_ = -1;
layout_t zp_layout_;
layout_t src_layout_;
layout_t wei_layout_;
layout_t comp_layout_;
zp_comp_kind_t kind_ = zp_comp_kind_t::undef;
int simd_dim_idx_ = -1; // comp layout index.
int simd_ = -1;
int split_factor_ = 1;
};
struct texpr_t {
texpr_t() {
std::fill(vidxs, vidxs + max_nvargs, -1);
std::fill(vstrides, vstrides + max_nvargs, 0);
}
expr_t to_expr(const std::vector<expr_t> &vvars) const {
auto ret = base;
for (int i = 0; i < nvargs(); i++) {
ret += vstrides[i] * vvars[vidxs[i]];
}
return ret;
}
expr_t to_expr(const std::vector<expr_t> &vstart,
const std::vector<dim_t> &vstart_inc,
const std::vector<expr_t> &vvars, int simd_vidx) const {
int ndims = (int)vstart.size();
gpu_assert((int)vstart_inc.size() == ndims);
gpu_assert((int)vvars.size() == ndims);
bool non_linear[max_nvdims] = {false};
if (has_non_linear) {
auto vars = find_objects<var_t>(base);
for (auto &v : vars) {
for (int i = 0; i < (int)vvars.size(); i++) {
if (vvars[i].is_same(v)) {
gpu_assert(i < max_nvdims);
non_linear[i] = true;
break;
}
}
}
}
gpu_assert(!non_linear[simd_vidx]);
auto ret = base;
for (int i = 0; i < nvargs(); i++) {
auto &s = vstart[vidxs[i]];
auto &s_inc = vstart_inc[vidxs[i]];
if (!is_zero(s)) ret += s * vstrides[i];
if (s_inc != 0) ret += s_inc * vstrides[i];
}
if (has_non_linear) {
for (int i = 0; i < ndims; i++) {
if (!non_linear[i]) continue;
ret = substitute(ret, vvars[i], vstart[i] + vstart_inc[i]);
}
}
return ret;
}
bool is_const() const { return nvargs() == 0 && jit::is_const(base); }
bool is_var() const { return nvargs() == 1 && is_zero(base); }
int64_t to_const() const {
gpu_assert(is_const());
return to_cpp<int64_t>(base);
}
bool has_vidx(int vidx, const std::vector<expr_t> &vvars) const {
for (int i = 0; i < nvargs(); i++)
if (vidxs[i] == vidx) return true;
if (has_non_linear) {
auto vars = find_objects<var_t>(base);
for (auto &v : vars) {
if (v.is_same(vvars[vidx])) return true;
}
}
return false;
}
dim_t vstride(int vidx) const {
for (int i = 0; i < nvargs(); i++)
if (vidxs[i] == vidx) { return vstrides[i]; }
gpu_error_not_expected() << "Dimension not found: " << vidx;
return -1;
}
texpr_t operator+(const texpr_t &b) const { return add(b, 1); }
texpr_t operator-(const texpr_t &b) const { return add(b, -1); }
texpr_t add(const texpr_t &b, int mult) const {
auto ret = *this;
if (mult == 1) {
ret.base += b.base;
} else {
ret.base -= b.base;
}
int cur_idx = nvargs();
for (int i = 0; i < b.nvargs(); i++) {
bool found = false;
for (int j = 0; j < nvargs(); j++) {
if (b.vidxs[i] == vidxs[j]) {
found = true;
ret.vstrides[j] += mult * b.vstrides[i];
break;
}
}
if (!found) {
gpu_assert(cur_idx < max_nvargs);
ret.vidxs[cur_idx] = b.vidxs[i];
ret.vstrides[cur_idx] += mult * b.vstrides[i];
cur_idx++;
}
}
ret.has_non_linear |= b.has_non_linear;
return ret;
}
texpr_t operator*(const texpr_t &b) const {
if (!is_const() && b.is_const()) return b * *this;
if (!is_const()) gpu_error_not_expected();
auto c = to_const();
auto ret = b;
ret.base *= c;
for (int i = 0; i < ret.nvargs(); i++)
ret.vstrides[i] *= c;
ret.has_non_linear |= has_non_linear;
return ret;
}
int nvargs() const {
for (int i = max_nvargs - 1; i >= 0; i--) {
if (vidxs[i] != -1) return i + 1;
}
return 0;
}
std::string str() const {
std::ostringstream oss;
std::vector<std::string> parts;
if (!is_zero(base)) parts.push_back(base.str());
for (int i = 0; i < nvargs(); i++) {
auto s = "_" + std::to_string(vidxs[i]);
// NOLINTNEXTLINE(performance-inefficient-string-concatenation)
if (vstrides[i] != 1) s = std::to_string(vstrides[i]) + " x " + s;
parts.push_back(std::move(s));
}
for (int i = 0; i < (int)parts.size(); i++) {
if (i > 0) oss << " + ";
oss << parts[i];
}
if (parts.empty()) return "0";
return oss.str();
}
IR_DEFINE_DUMP()
static texpr_t create_from_const(const expr_t &e) {
gpu_assert(jit::is_const(e));
texpr_t ret;
ret.base = e;
return ret;
}
static texpr_t create_from_vidx(int vidx) {
gpu_assert(vidx != -1);
texpr_t ret;
ret.base = expr_t(0);
ret.vidxs[0] = vidx;
ret.vstrides[0] = 1;
return ret;
}
static const int max_nvargs = 2;
static const int max_nvdims = 16;
expr_t base;
int vidxs[max_nvargs];
int64_t vstrides[max_nvargs];
bool has_non_linear = false;
};
class zp_mask_desc_t {
public:
zp_mask_desc_t(const expr_t &mask, const std::vector<expr_t> &vvars,
const std::vector<expr_t> &vstart) {
vinfo_t vinfo(vvars, vstart);
if (is_x_op_y(mask, vinfo, op_, lhs_, rhs_)) return;
gpu_error_not_expected() << mask;
}
const texpr_t &lhs() const { return lhs_; }
const texpr_t &rhs() const { return rhs_; }
expr_t normalize(const std::vector<expr_t> &vvars,
const std::vector<expr_t> &vstart,
const std::vector<dim_t> &vstart_inc, int simd,
int simd_vidx) const {
auto e_lhs = lhs_.to_expr(vstart, vstart_inc, vvars, simd_vidx);
auto e_rhs = rhs_.to_expr(vstart, vstart_inc, vvars, simd_vidx);
e_lhs = shuffle_t::make_broadcast(e_lhs, simd);
e_rhs = shuffle_t::make_broadcast(e_rhs, simd);
if (!lhs_.has_vidx(simd_vidx, vvars)) {
return binary_op_t::make(op_, e_lhs, e_rhs);
}
dim_t stride = lhs_.vstride(simd_vidx);