xe: jit: address clang-tidy complaints

Author: atkassen

src/gpu/intel/jit/conv/pipeline.cpp

@@ -622,9 +622,9 @@ struct compute_params_t {
         : slm_bufs(slm_bufs)
         , gmem_bufs(gmem_bufs)
         , slm_buf_size(slm_buf_size)
-        , prefetch_bufs(prefetch_bufs) {
-        use_slm = (slm_buf_size > 0);
-        use_prefetch = (prefetch_bufs > 0);
+        , prefetch_bufs(prefetch_bufs)
+        , use_slm(slm_buf_size > 0)
+        , use_prefetch(prefetch_bufs > 0) {
         gpu_assert(!use_slm || !use_prefetch)
                 << "Can't have both SLM buffering and prefetch enabled.";
         if (use_slm) {

src/gpu/intel/jit/conv/plan.cpp

@@ -1263,17 +1263,16 @@ struct fma_layout_hint_t {
 };
 
 struct fma_context_t {
-    fma_context_t(const conv_config_t &cfg) {
-        hw = cfg.hw();
-        simd = cfg.simd();
-        vec_size = cfg.vec_size();
-        fma = cfg.fma_kind();
-        a_type = type_t(cfg.prb().a_data_type);
-        b_type = type_t(cfg.prb().b_data_type);
-        acc_type = get_accumulation_type(cfg, a_type, b_type);
-        is_src1_broadcast = !cfg.prb().is_dw;
-        ab_swap_transpose_ = cfg.prb().ab_swap_transpose;
-    }
+    fma_context_t(const conv_config_t &cfg)
+        : hw(cfg.hw())
+        , simd(cfg.simd())
+        , vec_size(cfg.vec_size())
+        , fma(cfg.fma_kind())
+        , a_type(cfg.prb().a_data_type)
+        , b_type(cfg.prb().b_data_type)
+        , acc_type(get_accumulation_type(cfg, a_type, b_type))
+        , is_src1_broadcast(!cfg.prb().is_dw)
+        , ab_swap_transpose_(cfg.prb().ab_swap_transpose) {}
 
     fma_layout_hint_t &layout_hint(abc_kind_t abc) {
         return (abc == abc_kind_t::a) ? a_layout_hint : b_layout_hint;

src/gpu/intel/jit/conv/tiler.cpp

@@ -597,7 +597,8 @@ class conv_blocking_checker_t : public blocking_checker_t {
 
 private:
     struct context_t {
-        context_t(const blocking_t &blk, const conv_config_t &cfg) : blk(blk) {
+        context_t(const blocking_t &blk, const conv_config_t &cfg)
+            : blk(blk), dpas_2x_depth(get_dpas_2x_depth(blk, cfg)) {
             auto &prb = cfg.prb();
             auto gemm_iter = to_gemm(blk.iter(), prb);
             auto gemm_loop = to_gemm(blk.loop(), prb);
@@ -611,7 +612,6 @@ class conv_blocking_checker_t : public blocking_checker_t {
             m_tg = gemm_tg.get(pvars::m, 1);
             n_tg = gemm_tg.get(pvars::n, 1);
             k_tg = gemm_tg.get(pvars::k, 1);
-            dpas_2x_depth = get_dpas_2x_depth(blk, cfg);
         }
 
         bool get_dpas_2x_depth(

src/gpu/intel/jit/ir/core.hpp

@@ -869,6 +869,7 @@ class ir_mutator_t {
     template <typename T>
     std::vector<T> mutate(const std::vector<T> &v) {
         std::vector<T> new_v;
+        new_v.reserve(v.size());
         for (auto &e : v)
             new_v.push_back(mutate(e));
         return new_v;

src/gpu/intel/jit/ir/epilogue.cpp

@@ -1030,6 +1030,7 @@ class epilogue_builder_t {
 
         // Create sub-tensors for post-ops.
         std::vector<post_op_tensor_t> sub_po_tensors;
+        sub_po_tensors.reserve(post_op_tensors_.size());
         for (auto &t : post_op_tensors_)
             sub_po_tensors.push_back(t.create_sub_tensor(tile));
 

src/gpu/intel/jit/ir/ir.cpp

@@ -387,7 +387,7 @@ class alloc_injector_t : public ir_mutator_t {
         buf_total_refs_ = buf_cur_refs_;
         for (auto &kv : buf_cur_refs_)
             kv.second = 0;
-        in_ctor_ = false;
+        in_ctor_ = false; // NOLINT(cppcoreguidelines-prefer-member-initializer)
     }
 
 #define HANDLE_IR_OBJECT(type) \

src/gpu/intel/jit/ir/message_patterns.hpp

@@ -500,7 +500,7 @@ struct uniform_send_idiom_t final {
                 ret.begin(), ret.end(), [&](const hint_t &a, const hint_t &b) {
                     return a.size() > b.size();
                 });
-        if (ret.size() && filtered_ret.size()
+        if (!ret.empty() && !filtered_ret.empty()
                 && ret[0].size() > filtered_ret[0].size())
             gpu_warning() << "Optimal send hint disabled: " << ret[0];
 

src/gpu/intel/jit/ir/send_plan.cpp

@@ -348,9 +348,11 @@ class tdim_info_t {
     tdim_info_t() = default;
     tdim_info_t(
             int tidx, const tdim_t &tdim, const view_t &view, int64_t block = 1)
-        : tidx_(tidx), block_(block), dim_(&tdim) {
-        base_mod_ = to_base(tdim, view.vvars());
-        size_ = view.tlayout().dim(tidx);
+        : tidx_(tidx)
+        , size_(view.tlayout().dim(tidx))
+        , base_mod_(to_base(tdim, view.vvars()))
+        , block_(block)
+        , dim_(&tdim) {
         for (dim_idx_t i = 0; i < tdim.nvargs(); i++) {
             vidxs_[i] = tdim.vidx(i);
             vstrides_[i] = tdim.vstride(i);
@@ -1810,10 +1812,10 @@ class view_iterator_t {
 public:
     view_iterator_t(const view_info_t &info)
         : info_(info)
+        , inner_elems_(1)
         , block_off_(nblocks())
         , block_dims_(nblocks())
         , off_(info.vlayout().ndims()) {
-        inner_elems_ = 1;
         for (int i = 0; i < info_.inner_idx(); i++) {
             inner_elems_ *= (int)blocks()[i].block;
         }

src/gpu/intel/jit/pass/hoist.cpp

@@ -83,6 +83,7 @@ class hoist_exprs_mutator_t : public ir_mutator_t {
         if (!obj.func.is<send_t>()) return ir_mutator_t::_mutate(obj);
 
         std::vector<expr_t> new_args;
+        new_args.reserve(obj.args.size());
         for (auto &e : obj.args) {
             new_args.push_back(hoist_expr(e));
         }
@@ -379,7 +380,7 @@ class hoist_send_masks_mutator_t : public ir_mutator_t {
         return loop_deps_.count(v) != 0;
     }
 
-    bool can_hoist(const expr_t &expr) {
+    bool can_hoist(const expr_t &expr) const {
         return expr.type().size() <= max_hoist_size_ - current_hoist_size_;
     }
 

src/gpu/intel/jit/pass/send.cpp

@@ -27,7 +27,7 @@ namespace jit {
 
 class buffer_offset_lifter_t : public ir_mutator_t {
 public:
-    object_t _mutate(const func_call_t &obj) {
+    object_t _mutate(const func_call_t &obj) override {
         if (!obj.func.is<send_t>()) return ir_mutator_t::_mutate(obj);
 
         auto &mem_buf = send_t::arg_mem_buf(obj);
@@ -56,7 +56,7 @@ class send_injector_t : public ir_mutator_t {
 public:
     send_injector_t(ir_context_t &ir_ctx) : ir_ctx_(ir_ctx) {}
 
-    object_t _mutate(const func_call_t &obj) {
+    object_t _mutate(const func_call_t &obj) override {
         auto *send = obj.func.as_ptr<send_t>();
         if (!send) return ir_mutator_t::_mutate(obj);
 
@@ -176,7 +176,7 @@ class send_2d_header_store_lifter_t : public ir_mutator_t {
                     off, send_t::header_2d_off_x(), send_t::header_2d_off_y())
                 && !is_const(obj.value))
             return obj;
-        stores_[obj.buf].push_back(obj);
+        stores_[obj.buf].emplace_back(obj);
         return stmt_t();
     }
 

src/gpu/intel/jit/pass/simplify.cpp

@@ -1565,6 +1565,7 @@ expr_t simplify_with_nary(const expr_t &_e, const constraint_set_t &cset) {
     return e;
 }
 
+// NOLINTNEXTLINE(readability-identifier-naming)
 class _64_bit_add_optimizer_t : public nary_op_mutator_t {
 public:
     object_t _mutate(const nary_op_t &obj) override {
@@ -1770,7 +1771,7 @@ struct op_traits_t {};
         static auto compute(T a, T b) -> decltype(a op b) { \
             return a op b; \
         } \
-        template <op_kind_t dummy_op = name, \
+        template <op_kind_t dummy_op = (name), \
                 typename = typename std::enable_if<dummy_op == op_kind_t::_and \
                         || dummy_op == op_kind_t::_or>::type> \
         static bool compute(bool a, bool b) { \

src/gpu/intel/jit/v2/conv/bridge.hpp

@@ -105,7 +105,7 @@ inline jit::layout_t to_conv_layout(const layout_tag_t &_tag,
 inline jit::layout_t to_conv_layout(
         const layout_tag_t &_tag, const pvar_tile_t &shape) {
     int ndims = _tag.desc().ndims();
-    auto tag = _tag.raw_tag();
+    const auto &tag = _tag.raw_tag();
     std::vector<dim_t> dims(ndims);
     for (int i = 0; i < ndims; i++) {
         auto d = _tag.desc().prb_dim(i);

src/gpu/intel/jit/v2/conv/debug.hpp

@@ -48,9 +48,9 @@ class debug_t {
             *desc_ptr_ = desc;
         }
 
-        kernel_desc_setter_t(kernel_desc_setter_t &&other) {
-            desc_ptr_ = other.desc_ptr_;
-            other.desc_ptr_ = nullptr;
+        kernel_desc_setter_t(kernel_desc_setter_t &&other)
+            : desc_ptr_(nullptr) {
+            std::swap(desc_ptr_, other.desc_ptr_);
         }
         kernel_desc_setter_t &operator=(kernel_desc_setter_t &&other) {
             if (&other != this) std::swap(desc_ptr_, other.desc_ptr_);

src/gpu/intel/jit/v2/conv/kernel_desc.hpp

@@ -78,7 +78,7 @@ static auto specialization_mode_names = nstl::to_array({
 GPU_DEFINE_PARSE_ENUM(specialization_mode_t, specialization_mode_names)
 
 struct specialization_t {
-    specialization_mode_t mode;
+    specialization_mode_t mode = specialization_mode_t::none;
     // Dimension values to specialize (e.g. kw1).
     pvar_tile_t dim_values;
     // Dimension modulus to specialize (e.g. oc@64)

src/gpu/intel/jit/v2/conv/plan_registry.hpp

@@ -55,7 +55,7 @@ class plan_registry_t {
     void stringify(std::ostream &out) const;
     void parse(std::istream &out);
 
-public:
+private:
     std::vector<entry_t> entries_;
 };
 

src/gpu/intel/jit/v2/conv/planner/bench.hpp

@@ -71,15 +71,16 @@ struct bench_input_params_t {
     bench_input_params_t() = default;
     bench_input_params_t(const kernel_desc_t &kernel_desc, const hw_t &hw,
             int nprbs = default_nprbs)
-        : hw(hw), nprbs(nprbs) {
-        prop = kernel_desc.prop;
-        src_tag = kernel_desc.src_tag;
-        wei_tag = kernel_desc.wei_tag;
-        dst_tag = kernel_desc.dst_tag;
-        reqs = kernel_desc.reqs();
-        is_dw = kernel_desc.is_dw;
-        bias_type = kernel_desc.bias_type;
-        tile = kernel_desc.iter_tile;
+        : hw(hw)
+        , prop(kernel_desc.prop)
+        , src_tag(kernel_desc.src_tag)
+        , wei_tag(kernel_desc.wei_tag)
+        , dst_tag(kernel_desc.dst_tag)
+        , reqs(kernel_desc.reqs())
+        , is_dw(kernel_desc.is_dw)
+        , bias_type(kernel_desc.bias_type)
+        , tile(kernel_desc.iter_tile)
+        , nprbs(nprbs) {
         for (auto &d : kernel_desc.thread_group_tile) {
             tile[d] = tile.get(d, 1) * kernel_desc.thread_group_tile[d];
         }

src/gpu/intel/jit/v2/conv/planner/search.cpp

@@ -447,6 +447,7 @@ class kernel_search_manager_t {
             }
         }
         std::vector<search_kernel_desc_group_t> ret;
+        ret.reserve(desc_groups.size());
         for (auto &kv : desc_groups) {
             ret.push_back(kv.second);
         }

src/gpu/intel/jit/v2/conv/problem.hpp

@@ -104,7 +104,7 @@ class problem_t {
     layout_tag_t dst_tag_;
     type_t bias_type_;
     pvar_tile_t shape_;
-    std::array<int, 3> dhw_map_;
+    std::array<int, 3> dhw_map_ = {0};
     bool with_groups_ = false;
     bool with_scales_ = false;
     bool with_post_ops_ = false;

src/gpu/intel/jit/v2/conv/tensor_utils.cpp

@@ -188,7 +188,7 @@ std::string blocked_to_str_tag(const memory_desc_t &md) {
     for (int i = blk.inner_nblks - 1; i >= 0; i--) {
         dim_idx_t idx = into<dim_idx_t>(blk.inner_idxs[i]);
         dim_t block = blk.inner_blks[i];
-        parts.push_back(std::string(1, dim_idx::as_tag(idx)));
+        parts.emplace_back(1, dim_idx::as_tag(idx));
         parts.push_back(std::to_string(block));
         full_inner_blks[idx] *= block;
         stride *= block;
@@ -211,7 +211,7 @@ std::string blocked_to_str_tag(const memory_desc_t &md) {
                 // Size-one blocks have to be added first.
                 if (min_dim == 1 && rem_dims[j] != min_dim) continue;
                 bool is_blocked = (full_inner_blks[j] != 1);
-                parts.push_back(std::string(1, dim_idx::as_tag(j, is_blocked)));
+                parts.emplace_back(1, dim_idx::as_tag(j, is_blocked));
                 stride *= rem_dims[j];
                 seen[j] = true;
                 found = true;

src/gpu/intel/ocl/gemm/gemm_with_post_ops.hpp

@@ -48,7 +48,7 @@ struct gemm_with_post_ops_t : public gpu_gemm_t {
         bool use_reorder = false;
         compute::dispatch_t dispatch_;
         attr_info_t attr_info_;
-        bool subbyte_pack_;
+        bool subbyte_pack_ = false;
     };
 
     status_t init(impl::engine_t *engine) override {

src/gpu/intel/ocl/reduction/combined_reduction.cpp

@@ -85,6 +85,7 @@ reduction_phase_conf_t::reduction_phase_conf_t(
     gpu_assert(reduction_block.block != 0) << "Reducing over 0 elements";
     if (outer_block.block == 0 || inner_block.block == 0) {
         nd_range = compute::nd_range_t({0}, {into<size_t>(subgroup_size)});
+        with_block_reads = false;
         return;
     }
     with_block_reads = can_use_block_reads();