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AD2605dzarukin
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Co-authored-by: Dmitry Zarukin <dmitry.zarukin@intel.com>
1 parent 886bdc7 commit 9008b9d

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+4
-7
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src/gpu/generic/sycl/ref_reorder.hpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -99,7 +99,7 @@ struct ref_reorder_t : public gpu::generic::sycl::primitive_t {
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bool scales_ok() const {
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if (!attr()->scales_.has_default_values(
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DNNL_ARG_ATTR_SCALES | DNNL_ARG_FROM)) {
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DNNL_ARG_FROM)) {
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// Check if scales are applied and then check the data type
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// otherwise either data type can come up as data_type::undef
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// returning false unecessarily

src/gpu/generic/sycl/reorder_kernels.hpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -44,9 +44,9 @@ struct reorder_kernel_t {
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, dst_scale_(
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CTX_IN_SYCL_KERNEL_MEMORY(DNNL_ARG_ATTR_SCALES | DNNL_ARG_TO))
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, src_zero_points(CTX_IN_SYCL_KERNEL_MEMORY(
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DNNL_ARG_ATTR_ZERO_POINTS | DNNL_ARG_SRC))
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DNNL_ARG_ATTR_ZERO_POINTS | DNNL_ARG_FROM))
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, dst_zero_points(CTX_IN_SYCL_KERNEL_MEMORY(
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DNNL_ARG_ATTR_ZERO_POINTS | DNNL_ARG_DST))
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DNNL_ARG_ATTR_ZERO_POINTS | DNNL_ARG_TO))
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, scales_src_dt_(conf_.do_scale_src
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? ctx.memory_mdw(DNNL_ARG_ATTR_SCALES | DNNL_ARG_FROM)
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.data_type()

tests/benchdnn/reorder/reorder.cpp

+1-4
Original file line numberDiff line numberDiff line change
@@ -356,10 +356,7 @@ void skip_unimplemented_prb(const prb_t *prb, res_t *res) {
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}
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// Skip blocked format tags and 4 bit formats for Nvidia/AMD/Generic SYCL backends
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const auto &engine = get_test_engine();
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if (is_generic_gpu(engine) || is_nvidia_gpu(engine)
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|| is_amd_gpu(engine)) {
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if (is_generic_gpu()) {
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const bool is_4bit_format = is_nibble_sized_type(prb->sdt)
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|| is_nibble_sized_type(prb->ddt);
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