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vic20nano_tp20k.gprj
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<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
<Template>FPGA</Template>
<Version>5</Version>
<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
<FileList>
<File path="src/c1541/mist_sd_card.sv" type="file.verilog" enable="1"/>
<File path="src/dualshock2.v" type="file.verilog" enable="1"/>
<File path="src/gowin_dpb/gowin_dpb_track_buffer_b.v" type="file.verilog" enable="1"/>
<File path="src/gowin_dpb/gowin_dpb_trkbuf.v" type="file.verilog" enable="1"/>
<File path="src/gowin_dpb/sector_dpram.v" type="file.verilog" enable="1"/>
<File path="src/hdmi/audio_clock_regeneration_packet.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi/audio_info_frame.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi/audio_sample_packet.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi/auxiliary_video_information_info_frame.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi/hdmi.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi/packet_assembler.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi/packet_picker.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi/serializer.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi/source_product_description_info_frame.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi/tmds_channel.sv" type="file.verilog" enable="1"/>
<File path="src/loader_sd_card.sv" type="file.verilog" enable="1"/>
<File path="src/megacart.v" type="file.verilog" enable="1"/>
<File path="src/megacart_nvram.v" type="file.verilog" enable="1"/>
<File path="src/misc/flash_dspi.v" type="file.verilog" enable="1"/>
<File path="src/misc/hid.v" type="file.verilog" enable="1"/>
<File path="src/misc/mcu_spi.v" type="file.verilog" enable="1"/>
<File path="src/misc/osd_u8g2.v" type="file.verilog" enable="1"/>
<File path="src/misc/scandoubler.v" type="file.verilog" enable="1"/>
<File path="src/misc/sd_card.v" type="file.verilog" enable="1"/>
<File path="src/misc/sd_rw.v" type="file.verilog" enable="1"/>
<File path="src/misc/sdcmd_ctrl.v" type="file.verilog" enable="1"/>
<File path="src/misc/sysctrl.v" type="file.verilog" enable="1"/>
<File path="src/misc/video.v" type="file.verilog" enable="1"/>
<File path="src/misc/video_analyzer.v" type="file.verilog" enable="1"/>
<File path="src/misc/ws2812.v" type="file.verilog" enable="1"/>
<File path="src/tang/primer20k/ddr3_controller.v" type="file.verilog" enable="1"/>
<File path="src/tang/primer20k/ddr3_tester.v" type="file.verilog" enable="1"/>
<File path="src/tang/primer20k/memory_controller.v" type="file.verilog" enable="1"/>
<File path="src/tang/primer20k/memtest.sv" type="file.verilog" enable="1"/>
<File path="src/c1530.vhd" type="file.vhdl" enable="1"/>
<File path="src/c1541/c1541_logic.vhd" type="file.vhdl" enable="1"/>
<File path="src/c1541/c1541_sd.vhd" type="file.vhdl" enable="1"/>
<File path="src/c1541/gcr_floppy.vhd" type="file.vhdl" enable="1"/>
<File path="src/c1541/via6522.vhd" type="file.vhdl" enable="1"/>
<File path="src/fifo_sc_hs/fifo_sc_hs.vhd" type="file.vhdl" enable="1"/>
<File path="src/gowin_dpb/gowin_dpb_1k.vhd" type="file.vhdl" enable="1"/>
<File path="src/gowin_dpb/gowin_dpb_1k_x4.vhd" type="file.vhdl" enable="1"/>
<File path="src/gowin_dpb/gowin_dpb_2k.vhd" type="file.vhdl" enable="1"/>
<File path="src/gowin_dpb/gowin_dpb_8k.vhd" type="file.vhdl" enable="1"/>
<File path="src/gowin_prom/gowin_prom_basic.vhd" type="file.vhdl" enable="1"/>
<File path="src/gowin_prom/gowin_prom_char.vhd" type="file.vhdl" enable="1"/>
<File path="src/gowin_sdpb/gowin_sdpb_kernal_8k.vhd" type="file.vhdl" enable="1"/>
<File path="src/gowin_sp/gowin_sp_2k.vhd" type="file.vhdl" enable="1"/>
<File path="src/gowin_sp/gowin_sp_8k.vhd" type="file.vhdl" enable="1"/>
<File path="src/m6522.vhd" type="file.vhdl" enable="1"/>
<File path="src/m6561.vhd" type="file.vhdl" enable="1"/>
<File path="src/ram_conf_1024x4.vhd" type="file.vhdl" enable="1"/>
<File path="src/ram_conf_1024x8.vhd" type="file.vhdl" enable="1"/>
<File path="src/ram_conf_2048x8.vhd" type="file.vhdl" enable="1"/>
<File path="src/ram_conf_8192x8.vhd" type="file.vhdl" enable="1"/>
<File path="src/t65/T65.vhd" type="file.vhdl" enable="1"/>
<File path="src/t65/T65_ALU.vhd" type="file.vhdl" enable="1"/>
<File path="src/t65/T65_MCode.vhd" type="file.vhdl" enable="1"/>
<File path="src/t65/T65_Pack.vhd" type="file.vhdl" enable="1"/>
<File path="src/tang/primer20k/vic20nano_top_tp20k.vhd" type="file.vhdl" enable="1"/>
<File path="src/vic20.vhd" type="file.vhdl" enable="1"/>
<File path="src/vic20_clocks.vhd" type="file.vhdl" enable="1"/>
<File path="src/vic20_keyboard.vhd" type="file.vhdl" enable="1"/>
<File path="src/tang/primer20k/vic20nano_top_tp20k.cst" type="file.cst" enable="1"/>
<File path="src/tang/primer20k/vic20nano_top_tp20k.sdc" type="file.sdc" enable="1"/>
</FileList>
</Project>