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Added support for VHDL and NVC and GHDL simulators, and for SystemVerilog DPI and Vivado and Verilator simulators.
1 parent 3043491 commit 96bf6dc

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‎README.md

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@@ -8,6 +8,10 @@ The mem_model component is a Verilog/VHDL simulation test component that allows
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A direct access API is also provided to allow any other PLI C/C++ code to transfer data directly, without the overhead of simulating bus transactions (see <tt>src/mem.h</tt>). Wrapper HDL is also provided to map the ports to an AXI subordinate interface (<tt>mem_model_axi.v</tt> and <tt>mem_model_axi.vhd</tt>). The default memory mapped slave port and burst ports are Altera Avalon bus compatible.
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By default memory is uninitialised but, if compiled with <tt>MEM_ZERO_NEW PAGES</tt> defined, memory will be initialised with zeros. By default, the model is big endian, but this can be overridden by defining <tt>MEM_MODEL_DEFAULT_ENDIAN=1</tt>.
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By default memory is uninitialised but, if compiled with <tt>MEM_ZERO_NEW_PAGES</tt> defined, memory will be initialised with zeros. By default, the model is big endian, but this can be overridden by defining <tt>MEM_MODEL_DEFAULT_ENDIAN=1</tt>.
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The model's software can be compiled for supporting various HDL languages, with the default being Verilog and using the PLI programming interface. To compile for the VPI interface, <tt>MEM_MODEL_PLI_VPI</tt> should be defined when compiling the <tt>mem_model.c</tt> code. When using VHDL then <tt>MEM_MODEL_VHDL</tt> should be defined. If using the SystemVerilog model then <tt>MEM_MODEL_SV</tt> should be defined. The model's code, when used with VProc, will also recognise the VProc definitions (<tt>VPROC_PLI_VPI</tt>, <tt>VPROC_VHDL</tt>, and <tt>VPROC_SV</tt>) and if these are defined when compiling the code, then the <tt>MEM_MODEL_XXX</tt> definitions do not need to be set which are needed only when compiling as a standalone model.
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If using Verilog or SystemVerilog models, then the <tt>tx_byteenable</tt> port is enabled by defining <tt>MEM_EN_TX_BYTEENABLE</tt> when analysing either <tt>mem_model.v</tt> or <tt>mem_model.sv</tt>.
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More details can be found in the manual&mdash;<tt>doc/mem_model_manual.pdf</tt>.

‎doc/mem_model_manual.pdf

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‎mem_model.sv

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@@ -0,0 +1,31 @@
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// ====================================================================
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//
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// SystemVerilog side mem_model
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//
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// Copyright (c) 2024 Simon Southwell.
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//
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// This file is part of mem_model.
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//
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// This file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// The file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this file. If not, see <http://www.gnu.org/licenses/>.
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//
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// ====================================================================
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// The SystemVerilog mem_model HDL is the same as the Verilog,
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// with MEM_MODEL_SV defined to select DPI-C over PLI
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`timescale 1ps / 1ps
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`define MEM_MODEL_SV
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`include "mem_model.v"

‎mem_model.v

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@@ -32,8 +32,21 @@
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//
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// -----------------------------------------------------------------------------
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`ifdef MEM_MODEL_SV
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`include "mem_model_dpi.vh"
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`define MEMREAD MemRead
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`define MEMWRITE MemWrite
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`else
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`timescale 1ps/1ps
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`define MEMREAD $memread
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`define MEMWRITE $memwrite
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`endif
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3750
module mem_model
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#(parameter
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EN_READ_QUEUE = 0
@@ -197,7 +210,7 @@ begin
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// If a slave read, return memory contents
198211
if (read == 1'b1 && readdatavalid == 1'b0)
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begin
200-
$memread(address, readdata, byteenable);
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`MEMREAD(address, readdata, byteenable);
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readdatavalid = 1'b1;
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end
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else
@@ -210,7 +223,7 @@ begin
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// If a slave write, update memory
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if (write == 1'b1)
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begin
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$memwrite(address, writedata, byteenable);
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`MEMWRITE(address, writedata, byteenable);
214227
end
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// If a new master read request comes in (and not active),
@@ -251,7 +264,7 @@ begin
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if (rx_count != 32'h00000000)
252265
begin
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254-
$memread(rd_addr, readdata_int, byteenable);
267+
`MEMREAD(rd_addr, readdata_int, byteenable);
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// Decrement the word count
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rx_count = rx_count - 32'h00000001;
@@ -264,7 +277,7 @@ begin
264277
// If an active write transfer in progress, transfer data
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if (tx_write == 1'b1 && tx_waitrequest == 1'b0 && tx_count != 32'h00000000)
266279
begin
267-
$memwrite(wr_addr, tx_writedata, tx_byteenable);
280+
`MEMWRITE(wr_addr, tx_writedata, tx_byteenable);
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// Decrement the word count
270283
tx_count = tx_count - 32'h00000001;
@@ -277,7 +290,7 @@ begin
277290
// If a write port access valid, write data
278291
if (wr_port_valid == 1'b1)
279292
begin
280-
$memwrite(wr_port_addr, wr_port_data, byteenable);
293+
`MEMWRITE(wr_port_addr, wr_port_data, byteenable);
281294
end
282295
end
283296
end

‎mem_model_axi.sv

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@@ -0,0 +1,31 @@
1+
// ====================================================================
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//
3+
// SystemVerilog side mem_model
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//
5+
// Copyright (c) 2024 Simon Southwell.
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//
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// This file is part of mem_model.
8+
//
9+
// This file is free software: you can redistribute it and/or modify
10+
// it under the terms of the GNU General Public License as published by
11+
// the Free Software Foundation, either version 3 of the License, or
12+
// (at your option) any later version.
13+
//
14+
// The file is distributed in the hope that it will be useful,
15+
// but WITHOUT ANY WARRANTY; without even the implied warranty of
16+
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17+
// GNU General Public License for more details.
18+
//
19+
// You should have received a copy of the GNU General Public License
20+
// along with this file. If not, see <http://www.gnu.org/licenses/>.
21+
//
22+
// ====================================================================
23+
24+
// The SystemVerilog mem_model HDL is the same as the Verilog,
25+
// with MEM_MODEL_SV defined to select DPI-C over PLI
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27+
`timescale 1ps / 1ps
28+
29+
`define MEM_MODEL_SV
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31+
`include "mem_model_axi.v"

‎mem_model_dpi.vh

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@@ -0,0 +1,32 @@
1+
// ====================================================================
2+
//
3+
// SystemVerilog DPI defintions for mem_model
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//
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// Copyright (c) 2024 Simon Southwell.
6+
//
7+
// This file is part of mem_model.
8+
//
9+
// VProc is free software: you can redistribute it and/or modify
10+
// it under the terms of the GNU General Public License as published by
11+
// the Free Software Foundation, either version 3 of the License, or
12+
// (at your option) any later version.
13+
//
14+
// VProc is distributed in the hope that it will be useful,
15+
// but WITHOUT ANY WARRANTY; without even the implied warranty of
16+
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17+
// GNU General Public License for more details.
18+
//
19+
// You should have received a copy of the GNU General Public License
20+
// along with VProc. If not, see <http://www.gnu.org/licenses/>.
21+
//
22+
// ====================================================================
23+
24+
// Import DPI-C fuctions
25+
26+
import "DPI-C" function void MemWrite (input int address,
27+
input int data,
28+
input int be);
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30+
import "DPI-C" function void MemRead (input int address,
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output int data,
32+
input int be);

‎mem_model_pkg_ghdl.vhd

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1+
-------------------------------------------------------------------------------
2+
-- Title : VHDL package for mem_model and GHDL simulator
3+
-- Project : UNKNOWN
4+
-------------------------------------------------------------------------------
5+
-- File : mem_model_pkg_nvc.vhd
6+
-- Author : Simon Southwell
7+
-- Created : 2024-09-21
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-- Platform :
9+
-- Standard : VHDL 2008
10+
-------------------------------------------------------------------------------
11+
-- Description:
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-- VHDL package for memory model, defining FLI procedures
13+
-------------------------------------------------------------------------------
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-- Copyright (c) 2024 Simon Southwell
15+
-------------------------------------------------------------------------------
16+
--
17+
-- This is free software: you can redistribute it and/or modify
18+
-- it under the terms of the GNU General Public License as published by
19+
-- the Free Software Foundation(), either version 3 of the License(), or
20+
-- (at your option) any later version.
21+
--
22+
-- It is distributed in the hope that it will be useful(),
23+
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
24+
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25+
-- GNU General Public License for more details.
26+
--
27+
-- You should have received a copy of the GNU General Public License
28+
-- along with this code. If not, see <http://www.gnu.org/licenses/>.
29+
--
30+
-------------------------------------------------------------------------------
31+
32+
library ieee;
33+
use ieee.std_logic_1164.all;
34+
35+
package mem_model_pkg is
36+
37+
type mem_array_t is array (natural range <>) of std_logic_vector;
38+
39+
procedure MemWrite (
40+
address : in integer;
41+
data : in integer;
42+
be : in integer
43+
);
44+
attribute foreign of MemWrite : procedure is "VHPIDIRECT ./VProc.so MemWrite";
45+
46+
procedure MemRead (
47+
address : in integer;
48+
data : out integer;
49+
be : in integer
50+
);
51+
attribute foreign of MemRead : procedure is "VHPIDIRECT ./VProc.so MemRead";
52+
53+
end;
54+
55+
package body mem_model_pkg is
56+
57+
procedure MemWrite (
58+
address : in integer;
59+
data : in integer;
60+
be : in integer
61+
) is
62+
begin
63+
report "ERROR: foreign subprogram out_params not called";
64+
end;
65+
66+
procedure MemRead (
67+
address : in integer;
68+
data : out integer;
69+
be : in integer
70+
) is
71+
begin
72+
report "ERROR: foreign subprogram out_params not called";
73+
end;
74+
75+
end;

‎mem_model_pkg_nvc.vhd

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@@ -0,0 +1,75 @@
1+
-------------------------------------------------------------------------------
2+
-- Title : VHDL package for mem_model and NVC simulator
3+
-- Project : UNKNOWN
4+
-------------------------------------------------------------------------------
5+
-- File : mem_model_pkg_nvc.vhd
6+
-- Author : Simon Southwell
7+
-- Created : 2024-09-21
8+
-- Platform :
9+
-- Standard : VHDL 2008
10+
-------------------------------------------------------------------------------
11+
-- Description:
12+
-- VHDL package for memory model, defining FLI procedures
13+
-------------------------------------------------------------------------------
14+
-- Copyright (c) 2024 Simon Southwell
15+
-------------------------------------------------------------------------------
16+
--
17+
-- This is free software: you can redistribute it and/or modify
18+
-- it under the terms of the GNU General Public License as published by
19+
-- the Free Software Foundation(), either version 3 of the License(), or
20+
-- (at your option) any later version.
21+
--
22+
-- It is distributed in the hope that it will be useful(),
23+
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
24+
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25+
-- GNU General Public License for more details.
26+
--
27+
-- You should have received a copy of the GNU General Public License
28+
-- along with this code. If not, see <http://www.gnu.org/licenses/>.
29+
--
30+
-------------------------------------------------------------------------------
31+
32+
library ieee;
33+
use ieee.std_logic_1164.all;
34+
35+
package mem_model_pkg is
36+
37+
type mem_array_t is array (natural range <>) of std_logic_vector;
38+
39+
procedure MemWrite (
40+
address : in integer;
41+
data : in integer;
42+
be : in integer
43+
);
44+
attribute foreign of MemWrite : procedure is "VHPIDIRECT MemWrite";
45+
46+
procedure MemRead (
47+
address : in integer;
48+
data : out integer;
49+
be : in integer
50+
);
51+
attribute foreign of MemRead : procedure is "VHPIDIRECT MemRead";
52+
53+
end;
54+
55+
package body mem_model_pkg is
56+
57+
procedure MemWrite (
58+
address : in integer;
59+
data : in integer;
60+
be : in integer
61+
) is
62+
begin
63+
report "ERROR: foreign subprogram out_params not called";
64+
end;
65+
66+
procedure MemRead (
67+
address : in integer;
68+
data : out integer;
69+
be : in integer
70+
) is
71+
begin
72+
report "ERROR: foreign subprogram out_params not called";
73+
end;
74+
75+
end;

‎src/mem_model.c

+4-4
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@@ -77,7 +77,7 @@ MEM_RTN_TYPE MemRead (MEM_READ_PARAMS)
7777
{
7878
uint32_t data_int, addr;
7979

80-
#if !defined(VPROC_VHDL) && !defined(SYSVLOG) && !defined(VPROC_PLI_VPI)
80+
#if !defined(VPROC_VHDL) && !defined(VPROC_SV) && !defined(VPROC_PLI_VPI)
8181
uint32_t address, be;
8282

8383
// Get address from $memread argument list
@@ -129,7 +129,7 @@ MEM_RTN_TYPE MemRead (MEM_READ_PARAMS)
129129
else
130130
data_int = ReadRamWord(address, MEM_MODEL_DEFAULT_ENDIAN, MEM_MODEL_DEFAULT_NODE);
131131

132-
#if defined(VPROC_VHDL) || defined(SYSVLOG)
132+
#if defined(VPROC_VHDL) || defined(VPROC_SV)
133133
*data = data_int;
134134
#else
135135
# if !defined (VPROC_PLI_VPI)
@@ -152,7 +152,7 @@ MEM_RTN_TYPE MemWrite (MEM_WRITE_PARAMS)
152152
{
153153
uint32_t addr;
154154

155-
#if !defined(VPROC_VHDL) && !defined(SYSVLOG) && !defined(VPROC_PLI_VPI)
155+
#if !defined(VPROC_VHDL) && !defined(VPROC_SV) && !defined(VPROC_PLI_VPI)
156156
uint32_t address, data, be;
157157

158158
// Get address from $memwrite argument list
@@ -205,7 +205,7 @@ MEM_RTN_TYPE MemWrite (MEM_WRITE_PARAMS)
205205
WriteRamWord(address, data, MEM_MODEL_DEFAULT_ENDIAN, MEM_MODEL_DEFAULT_NODE);
206206
}
207207

208-
#if !defined(VPROC_VHDL) && !defined(SYSVLOG) && !defined (VPROC_PLI_VPI)
208+
#if !defined(VPROC_VHDL) && !defined(VPROC_SV) && !defined (VPROC_PLI_VPI)
209209
return 0;
210210
#endif
211211
}

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