[ARM] ARM 32bits support for oneDNN

[ARM] double matches in cmake fix

Author: ilya-lavrenov

CMakeLists.txt

@@ -89,6 +89,8 @@ endif()
 if(NOT DNNL_TARGET_ARCH)
     if(CMAKE_SYSTEM_PROCESSOR MATCHES "^(aarch64.*|AARCH64.*|arm64.*|ARM64.*)")
         set(DNNL_TARGET_ARCH "AARCH64")
+    elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "^(arm.*|ARM.*)")
+        set(DNNL_TARGET_ARCH "ARM")
     elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "^(ppc64.*|PPC64.*|powerpc64.*)")
         set(DNNL_TARGET_ARCH "PPC64")
     elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "^(s390x.*|S390X.*)")

cmake/ACL.cmake

@@ -21,7 +21,7 @@ endif()
 set(acl_cmake_included true)
 include("cmake/options.cmake")
 
-if(NOT DNNL_TARGET_ARCH STREQUAL "AARCH64")
+if(NOT DNNL_TARGET_ARCH MATCHES "^(AARCH64|ARM)$")
     return()
 endif()
 

cmake/platform.cmake

@@ -234,7 +234,7 @@ elseif(UNIX OR MINGW)
     platform_unix_and_mingw_noexcept_ccxx_flags(CMAKE_CMAKE_CCXX_NOEXCEPT_FLAGS)
     # compiler specific settings
     if(CMAKE_CXX_COMPILER_ID MATCHES "Clang")
-        if(DNNL_TARGET_ARCH STREQUAL "AARCH64")
+        if(DNNL_TARGET_ARCH MATCHES "^(AARCH64|ARM)$")
              if (NOT CMAKE_BUILD_TYPE STREQUAL "Debug")
                  set(DEF_ARCH_OPT_FLAGS "-O3")
              endif()
@@ -339,7 +339,7 @@ elseif(UNIX OR MINGW)
             append(CMAKE_CCXX_FLAGS "-Wno-attributes")
         endif()
 
-        if(DNNL_TARGET_ARCH STREQUAL "AARCH64")
+        if(DNNL_TARGET_ARCH MATCHES "^(AARCH64|ARM)$")
             if (NOT CMAKE_BUILD_TYPE STREQUAL "Debug")
                 set(DEF_ARCH_OPT_FLAGS "-O3")
             endif()

include/oneapi/dnnl/dnnl_types.h

@@ -2292,7 +2292,12 @@ typedef enum {
 /// A `size_t` counterpart of the DNNL_RUNTIME_DIM_VAL.
 /// For instance, this value is returned by dnnl_memory_desc_get_size() if
 /// either of the dimensions or strides equal to #DNNL_RUNTIME_DIM_VAL.
+
+#if INTPTR_MAX == INT64_MAX
 #define DNNL_RUNTIME_SIZE_VAL ((size_t)DNNL_RUNTIME_DIM_VAL)
+#else
+#define DNNL_RUNTIME_SIZE_VAL ((size_t)INT32_MIN)
+#endif
 
 /// @cond DO_NOT_DOCUMENT_THIS
 /// Hex representation for a **special** quiet NAN (!= NAN from math.h)

src/common/utils.cpp

@@ -230,7 +230,7 @@ bool get_jit_dump() {
     return jit_dump.get();
 }
 
-#if defined(DNNL_AARCH64) && (DNNL_AARCH64 == 1)
+#if defined(DNNL_AARCH64) && (DNNL_AARCH64 == 1) || defined(DNNL_ARM) && (DNNL_ARM == 1)
 static setting_t<unsigned> jit_profiling_flags {DNNL_JIT_PROFILE_LINUX_PERFMAP};
 #else
 static setting_t<unsigned> jit_profiling_flags {DNNL_JIT_PROFILE_VTUNE};

src/cpu/README.md

@@ -44,7 +44,9 @@ architecture. Hence, for portability reasons [`cpu/platform.hpp`](platform.hpp)
 header file provides a set of helpers macros that could help conditionally
 enable or disable parts of code. There the following macros defined:
 - `DNNL_X64` is 1 on x64 architecture;
+- `DNNL_X86` is 1 on x86 architecture;
 - `DNNL_AARCH64` is 1 on Arm AArch64 architecture;
+- `DNNL_ARM` is 1 on Arm 32 architecture;
 - `DNNL_PPC64` is 1 on OpenPOWER / IBM Power architecture;
 - `DNNL_S390X` is 1 on IBMz / s390x architecture;
 - `DNNL_RV64` is 1 on RISC-V architecture;

src/cpu/cpu_engine.hpp

@@ -29,7 +29,7 @@
 
 #include "cpu/platform.hpp"
 
-#if DNNL_AARCH64 && DNNL_AARCH64_USE_ACL
+#if (DNNL_AARCH64 || DNNL_ARM) && DNNL_AARCH64_USE_ACL
 #include "cpu/aarch64/acl_thread.hpp"
 #endif
 
@@ -46,8 +46,11 @@
 #define CPU_INSTANCE_AVX512(...) REG_AVX512_ISA(CPU_INSTANCE(__VA_ARGS__))
 #define CPU_INSTANCE_AMX(...) REG_AMX_ISA(CPU_INSTANCE(__VA_ARGS__))
 #define CPU_INSTANCE_AARCH64(...) DNNL_AARCH64_ONLY(CPU_INSTANCE(__VA_ARGS__))
+#define CPU_INSTANCE_ARM(...) DNNL_ARM_ONLY(CPU_INSTANCE(__VA_ARGS__))
 #define CPU_INSTANCE_AARCH64_ACL(...) \
     DNNL_AARCH64_ACL_ONLY(CPU_INSTANCE(__VA_ARGS__))
+#define CPU_INSTANCE_ARM_ACL(...) \
+    DNNL_ARM_ACL_ONLY(CPU_INSTANCE(__VA_ARGS__))
 #define CPU_INSTANCE_RV64GCV(...) DNNL_RV64GCV_ONLY(CPU_INSTANCE(__VA_ARGS__))
 
 namespace dnnl {
@@ -160,7 +163,7 @@ class cpu_engine_factory_t : public engine_factory_t {
         *engine = new cpu_engine_t(new impl::engine_impl_t(
                 engine_kind::cpu, get_cpu_native_runtime(), 0));
 
-#if DNNL_AARCH64 && DNNL_AARCH64_USE_ACL
+#if (DNNL_AARCH64 || DNNL_ARM) && DNNL_AARCH64_USE_ACL
         dnnl::impl::cpu::aarch64::acl_thread_utils::set_acl_threading();
 #endif
         return status::success;

src/cpu/platform.cpp

@@ -205,8 +205,8 @@ unsigned get_per_core_cache_size(int level) {
 unsigned get_num_cores() {
 #if DNNL_X64
     return x64::cpu().getNumCores(Xbyak::util::CoreLevel);
-#elif DNNL_AARCH64_USE_ACL
-    return aarch64::cpu().getNumCores(Xbyak_aarch64::util::CoreLevel);
+#elif (DNNL_AARCH64 || DNNL_ARM) && DNNL_AARCH64_USE_ACL
+    return arm_compute::cpuinfo::num_threads_hint();
 #else
     return 1;
 #endif

src/cpu/platform.hpp

@@ -26,7 +26,9 @@
 
 // Possible architectures:
 // - DNNL_X64
+// - DNNL_X86
 // - DNNL_AARCH64
+// - DNNL_ARM
 // - DNNL_PPC64
 // - DNNL_S390X
 // - DNNL_RV64
@@ -35,12 +37,19 @@
 
 #if defined(DNNL_X64) + defined(DNNL_AARCH64) + defined(DNNL_PPC64) \
                 + defined(DNNL_S390X) + defined(DNNL_RV64) \
+                + defined(DNNL_ARM) + defined(DNNL_X86) \
                 + defined(DNNL_ARCH_GENERIC) \
         == 0
-#if defined(__x86_64__) || defined(_M_X64)
+#if defined(__amd64__) || defined(__amd64) || defined(__x86_64__) || \
+      defined(__x86_64) || defined(_M_X64) || defined(_M_AMD64)
 #define DNNL_X64 1
-#elif defined(__aarch64__)
+#elif defined(i386) || defined(__i386) || defined(__i386__) || defined(__IA32__) || defined(_M_I86) || \
+      defined(_M_IX86) || defined(__X86__) || defined(_X86_) || defined(__I86__) || defined(__386)
+#define DNNL_X86 1
+#elif defined(__aarch64__) || defined(_M_ARM64)
 #define DNNL_AARCH64 1
+#elif defined(__arm__) || defined(_M_ARM) || defined(__ARMEL__)
+#define DNNL_ARM 1
 #elif defined(__powerpc64__) || defined(__PPC64__) || defined(_ARCH_PPC64)
 #define DNNL_PPC64 1
 #elif defined(__s390x__)
@@ -54,6 +63,7 @@
 
 #if defined(DNNL_X64) + defined(DNNL_AARCH64) + defined(DNNL_PPC64) \
                 + defined(DNNL_S390X) + defined(DNNL_RV64) \
+                + defined(DNNL_ARM) + defined(DNNL_X86) \
                 + defined(DNNL_ARCH_GENERIC) \
         != 1
 #error One and only one architecture should be defined at a time
@@ -62,9 +72,15 @@
 #if !defined(DNNL_X64)
 #define DNNL_X64 0
 #endif
+#if !defined(DNNL_X86)
+#define DNNL_X86 0
+#endif
 #if !defined(DNNL_AARCH64)
 #define DNNL_AARCH64 0
 #endif
+#if !defined(DNNL_ARM)
+#define DNNL_ARM 0
+#endif
 #if !defined(DNNL_PPC64)
 #define DNNL_PPC64 0
 #endif
@@ -84,6 +100,7 @@
 #define DNNL_PPC64_ONLY(...) Z_CONDITIONAL_DO(DNNL_PPC64_ONLY, __VA_ARGS__)
 #define DNNL_S390X_ONLY(...) Z_CONDITIONAL_DO(DNNL_S390X_ONLY, __VA_ARGS__)
 #define DNNL_AARCH64_ONLY(...) Z_CONDITIONAL_DO(DNNL_AARCH64, __VA_ARGS__)
+#define DNNL_ARM_ONLY(...) Z_CONDITIONAL_DO(DNNL_ARM, __VA_ARGS__)
 
 // Using RISC-V implementations optimized with RVV Intrinsics is optional for RISC-V builds
 // and can be enabled with DNNL_ARCH_OPT_FLAGS="-march=<ISA-string>" option, where <ISA-string>
@@ -105,6 +122,14 @@
 #define DNNL_AARCH64_ACL_ONLY(...)
 #endif
 
+// Using Arm Compute Library kernels is optional for ARM builds
+// and can be enabled with the DNNL_AARCH64_USE_ACL CMake option
+#if defined(DNNL_ARM) && defined(DNNL_AARCH64_USE_ACL)
+#define DNNL_ARM_ACL_ONLY(...) __VA_ARGS__
+#else
+#define DNNL_ARM_ACL_ONLY(...)
+#endif
+
 // Primitive ISA section for configuring knobs.
 // Note: MSVC preprocessor by some reason "eats" symbols it's not supposed to
 // if __VA_ARGS__ is passed as empty. Then things happen like this for non-x64:

src/cpu/x64/cpu_isa_traits.hpp

@@ -374,11 +374,13 @@ namespace {
 static inline bool mayiuse(const cpu_isa_t cpu_isa, bool soft = false) {
     using namespace Xbyak::util;
 #if DNNL_X64
-    unsigned cpu_isa_mask = x64::get_max_cpu_isa_mask(soft);
+    const unsigned cpu_isa_mask = x64::get_max_cpu_isa_mask(soft);
+#elif DNNL_X86
+    const unsigned cpu_isa_mask = isa_undef;
 #else
-    unsigned cpu_isa_mask = isa_all;
+    const unsigned cpu_isa_mask = isa_all;
 #endif
-    unsigned cpu_isa_no_hints = cpu_isa & ~cpu_isa_hints_utils::hints_mask;
+    const unsigned cpu_isa_no_hints = cpu_isa & ~cpu_isa_hints_utils::hints_mask;
 
     if ((cpu_isa_mask & cpu_isa_no_hints) != cpu_isa_no_hints) return false;