Implement FIFO with procedures of writing/reading elements between master-slave interfaces of AXI4-protocol (My IPs)
The final construction (My IPs modifications) requires
- Construction of 64-fifo (32 bits size word)
- Implementation of procedures for recording and reading fifo elements between masters slave Interfaces of AXI4-protocol
The whole project is structured based on the diagram below:
Modules:
- Processing System (PS): The processor that runs the application and can communicate with PL via an I/O port.
- Interconnect (I/C): Interconnection that allows communication between modules.
- Memory ctlr: The memory controller that allows access to data from PS and any module in PL.
- Memory: The memory that data is stored either for processing or as results after processing.
- My IPs: All the logic we've put in and can access memory through DMAe. Probably logic not only communicates with DMAe, but also has a connection to PS, in order to be able to pass parameters or see the state of the Logic.
- DMA engine (DMAe): The module that allows access to memory without being affected
the operation of PS. More specifically, DMAe has the following signals:
- Configuration: Interface to enable the PS to program or view the status of DMAe
- Data_mem: Memory-mapped interface to exchange the DMAe data with the memory.
- Data_M2IP_S: Streaming interface for transferring data from DMAe to our logic.
- Data_IP2M_S: Streaming interface to transfer data from our logic to the DMAe.
Interconnection of PS with DMAe using AXI4 and AXI4 interface
Here, it's the block design at Vivado. Based on the numbers shown in the figure:
- The PS running the application, and will configure the DMAe
- The AXI4 interconnect that allows communication between the PS and our logic, one AXI4 memory controller, and DMAe.
- The 1st memory controller that allows access to memory from the PS
- The 2nd memory controller that allows access to memory from the DMAe
- The DMAe used to transfer data between logic <-> DMAe.
- The AXI4 interconnect that allows DMAe to access memory via memory controller.
- The memory in which data is stored for processing and results.
- Our logic.
In our logic, we have set the variables in the table below:
| Type | Name | Size (bits) | Type | Description |
|---|---|---|---|---|
| Slave AXI4 Stream Interface | S_Axis_tvalid | 1 | Input | Declare data existance for save in FIFO |
| -//- | S_Axis_tdata | 32 | Input | Data for save in FIFO |
| -//- | S_Axis_tread | 1 | Output | FIFO ready for new entry |
| Master AXI4 Stream Interface | M_Axis_tvalid | 1 | Output | Declare save data in FIFO from old entry |
| -//- | M_Axis_tdata | 32 | Output | Data saved in FIFO from old entry |
| -//- | M_Axis_tready | 1 | Input | DMAe is ready for new entry |
- Open the project with 2017.4
- Flow navigator -> IP catalog -> User repository -> AXI peripheral -> my ip -> Edit in IP packager 1
- A new instance of Vivado will open, where you will make the changes of the VHDL code.
- In the new project that opens -> Sources -> Design Sources -> myip_v1_1.vhd click to open the top level module code. By expanding myip_v1_1.vhd you will see the others two components that implement the AXI Stream master and slave interfaces.
- When you make changes to the code, then save. Then select Project Manager -> Package IP. A new tab appears on the right "Package IP - myip" along with Packaging steps.
- In the identification, change the version, so that you can be sure that after the simulation you use the updated IP.
- In the Review and Package step, click Re-Package IP. In the original project that is for the whole system, an IP catalog message will be displayed is out-of-date:
- Press Refresh IP Catalog and then at the bottom Upgrade selected. In the window "Generate Output Products" press Skip.
- If you already have the simulation open, you should start it from scratch.
- FIFO writing
if(S_Axis_tvalid==1 and S_AXIS_tready==1) then
FIFO[i] <= S_AXIS_tdata;
where i 1st empty space in FIFO
- FIFO reading
if(M_Axis_tvalid==1 and S_AXIS_tready==1) then
M_Axis_tdata <= FIFO[0];
- Change of counter/pointers and positions reserved for the construction of FIFO
- Modification of FSM machine in slave module for registration.
- Master-slave communication for reading with address signal.
- Insertion register in the slave component.
Simulations have been used that separately depict the functionality of the myip_module. Simulation are divided into two operating scenarios.
Read/Write without delay (scenario#1)
FIFO in reset state
Write
- Assign data for registration by the Slave interface (0, FIFO-Length-1)
s_tready = 1s_tvalid = 1
signal storetransfers data from register to FIFO- Data stream from zero to FIFO-Length-1
- In the last entry,
writes_doneis activated- the registration is completed.
Read
True signals: M_valid, M_tready
- Master forwards address to slave
- Slave takes data from FIFO[address] and forwards to master 2
- Terminations is when read pointer is on FIFO-Length
- 'tx_done = 1'
Read/Write with intervals (scenario#2)
FIFO in reset state Steps:
- The first assignment to be recorded by the Slave interface is made for 28 cycles.
- 5-cycle pause
- The second assignment to be recorded by the Slave interface is made for 36 cycles.
- 10-cycle pause
- The first read procedure between the two components for 28 cycles.
- 5-cycle pause
- The second read procedure between the two components for 36 cycles.
- Open the project with 2017.4
- IP INTEGRATOR -> Open Block Design
- SIMULATION -> Run Simulation -> Run Behavioral Simulation
- When the simulation opens, close the Untitled waveform (if any) and open it "tb_behav.wcfg" as follows: File -> Open Waveform Configuration -> tb_behav.wcfg
- To the left of the waveform there are the Obejcts and next to them 2 tabs, Scope and Resources. Select the Resources Simulation Sources sim_1 zynq_tb.v to open the testbench.
- Press the "Run all" button to run the simulation and once it is finished you can continue the simulation by pressing the "Run for 1000 ns" button to continue the simulation for 1000 nsec at a time.