boards: st: stm32n6570_dk: configure and enable sdmmc2

Configure and enable SDMMC2 for the STM32N6570-DK.
Also configure and enable the PLL2 and the IC4 to use them as a 48MHz
source clock for the SDMMC.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>

Author: gautierg-st

boards/st/stm32n6570_dk/doc/index.rst

@@ -87,6 +87,12 @@ Default Zephyr Peripheral Mapping:
 - I2C4_SDA : PE14
 - LD1 : PO1
 - LD2 : PG10
+- SDMMC2_CK : PC2
+- SDMMC2_CMD : PC3
+- SDMMC2_D0 : PC4
+- SDMMC2_D1 : PC5
+- SDMMC2_D2 : PC0
+- SDMMC2_D3 : PE4
 - SPI5_SCK : PE15
 - SPI5_MOSI : PG2
 - SPI5_MISO : PH8

boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi

@@ -59,6 +59,15 @@
 	status = "okay";
 };
 
+&pll2 {
+	clocks = <&clk_hsi>;
+	div-m = <4>;
+	mul-n = <24>;
+	div-p1 = <2>;
+	div-p2 = <2>;
+	status = "okay";
+};
+
 &ic1 {
 	pll-src = <1>;
 	ic-div = <2>;
@@ -71,6 +80,12 @@
 	status = "okay";
 };
 
+&ic4 {
+	pll-src = <2>;
+	ic-div = <2>;
+	status = "okay";
+};
+
 &ic6 {
 	pll-src = <1>;
 	ic-div = <2>;
@@ -140,6 +155,19 @@
 	status = "okay";
 };
 
+&sdmmc2 {
+	status = "okay";
+	clocks = <&rcc STM32_CLOCK(AHB5, 7)>,
+		 <&rcc STM32_SRC_IC4 SDMMC2_SEL(2)>;
+	pinctrl-0 = <&sdmmc2_d0_pc4 &sdmmc2_d1_pc5
+			&sdmmc2_d2_pc0 &sdmmc2_d3_pe4
+			&sdmmc2_ck_pc2 &sdmmc2_cmd_pc3>;
+	pinctrl-names = "default";
+	bus-width = <4>;
+	cd-gpios = <&gpion 8 GPIO_ACTIVE_HIGH>;
+	pwr-gpios = <&gpioq 7 GPIO_ACTIVE_HIGH>;
+};
+
 &spi5 {
 	clocks = <&rcc STM32_CLOCK(APB2, 20)>,
 		 <&rcc STM32_SRC_CKPER SPI5_SEL(1)>;