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boards: phytec: add support for phyBOARD-Atlas i.MX RT1170
Add initial support for PHYTEC phyBOARD-Atlas i.MX RT1170 based on the PHYTEC phyCORE-i.MX RT1170 SOM. SOM uses dual-core NXP i.MX RT1170 SoC as a basis, with Cortex-M7 core running at 1 GHz and Cortex-M4 core at 400 MHz. Supported features: * Accelerometer * Audio codec * CAN * DAC * EEPROM * Ethernet * External display * I2C * RS-232 * SD-Card * SPI * UART * USB Signed-off-by: John Ma <jma@phytec.com> Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Signed-off-by: Florijan Plohl <florijan.plohl@norik.com>
1 parent db6661d commit d929a25

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‎boards/phytec/phyboard_atlas/CMakeLists.txt

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if(CONFIG_NXP_IMXRT_BOOT_HEADER)
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zephyr_library()
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set(RT1170_BOARD_NAME "evkmimxrt1170")
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set(RT1170_BOARD_DIR
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"${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/${RT1170_BOARD_NAME}")
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if(CONFIG_BOOT_FLEXSPI_NOR)
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# Include flash configuration block for RT1170 EVK from NXP's HAL.
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# This configuration block may need modification if another flash chip is
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# used on your custom board. See NXP AN12238 for more information.
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zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1)
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zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024)
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zephyr_library_sources(flexspi_nor_config.c)
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endif()
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if(CONFIG_DEVICE_CONFIGURATION_DATA)
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# Include device configuration data block for RT1170 EVK from NXP's HAL.
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# This configuration block may need modification if another SDRAM chip
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# is used on your custom board.
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zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1)
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zephyr_library_sources(${RT1170_BOARD_DIR}/dcd.c)
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else()
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if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000)
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message(WARNING "You are using SDRAM as RAM but no device "
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"configuration data (DCD) is included. This configuration may not boot")
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endif()
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endif()
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endif()
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if(CONFIG_MCUX_GPT_TIMER)
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message(WARNING "You appear to be using the GPT hardware timer. "
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"This timer will enable lower power modes, but at the cost of reduced "
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"hardware timer resolution")
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endif()

‎boards/phytec/phyboard_atlas/Kconfig.defconfig

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# PHYBOARD-ATLAS
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# Copyright (c) 2025 PHYTEC America, LLC
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_PHYBOARD_ATLAS
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# Only use DCD when booting primary core (M7)
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config DEVICE_CONFIGURATION_DATA
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default y if CPU_CORTEX_M7
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config NXP_IMX_EXTERNAL_SDRAM
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default y if CPU_CORTEX_M7
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if SECOND_CORE_MCUX && CPU_CORTEX_M4
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config BUILD_OUTPUT_INFO_HEADER
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default y
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DT_CHOSEN_IMAGE_M4 = nxp,m4-partition
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# Adjust the offset of the output image if building for RT11xx SOC
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config BUILD_OUTPUT_ADJUST_LMA
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default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_M4)) + \
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$(dt_node_reg_addr_hex,/soc/spi@400cc000,1)) - \
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$(dt_node_reg_addr_hex,/soc/ocram@20200000)"
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endif # SECOND_CORE_MCUX && CPU_CORTEX_M4
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if NETWORKING
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config NET_L2_ETHERNET
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default y if CPU_CORTEX_M7 # No cache memory support is required for driver
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endif # NETWORKING
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if DISK_DRIVERS
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config IMX_USDHC_DAT3_PWR_TOGGLE
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default y
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endif # DISK_DRIVERS
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endif # BOARD_PHYBOARD_ATLAS

‎boards/phytec/phyboard_atlas/Kconfig.phyboard_atlas

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# Copyright 2025 PHYTEC America, LLC
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_PHYBOARD_ATLAS
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select SOC_MIMXRT1176_CM7 if BOARD_PHYBOARD_ATLAS_MIMXRT1176_CM7
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select SOC_MIMXRT1176_CM4 if BOARD_PHYBOARD_ATLAS_MIMXRT1176_CM4
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select SOC_PART_NUMBER_MIMXRT1176DVMAA

‎boards/phytec/phyboard_atlas/board.cmake

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if(CONFIG_SOC_MIMXRT1176_CM7 OR CONFIG_SECOND_CORE_MCUX)
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board_runner_args(pyocd "--target=mimxrt1170_cm7")
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board_runner_args(jlink "--device=MIMXRT1176xxxA_M7" "--reset-after-load")
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board_runner_args(linkserver "--device=MIMXRT1176xxxxx:MIMXRT1170-EVK")
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board_runner_args(linkserver "--core=cm7")
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elseif(CONFIG_SOC_MIMXRT1176_CM4)
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board_runner_args(pyocd "--target=mimxrt1170_cm4")
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# Note: Please use JLINK above V7.50 (Only support run cm4 image when debugging due to default boot core on board is cm7 core)
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board_runner_args(jlink "--device=MIMXRT1176xxxA_M4")
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board_runner_args(linkserver "--device=MIMXRT1176xxxxx:MIMXRT1170-EVK")
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board_runner_args(linkserver "--core=cm4")
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endif()
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)

‎boards/phytec/phyboard_atlas/board.yml

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board:
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name: phyboard_atlas
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full_name: phyBOARD-Atlas i.MX RT1170
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vendor: phytec
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socs:
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- name: mimxrt1176

‎boards/phytec/phyboard_atlas/doc/img/phyboard_atlas.webp

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‎boards/phytec/phyboard_atlas/doc/index.rst

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‎boards/phytec/phyboard_atlas/flexspi_nor_config.c

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/*
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* Copyright (c) 2025 PHYTEC America, LLC
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* All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <flexspi_nor_config.h>
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.xip_board"
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#endif
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/*******************************************************************************
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* Code
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******************************************************************************/
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#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
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#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
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__attribute__((section(".boot_hdr.conf"), used))
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#elif defined(__ICCARM__)
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#pragma location = ".boot_hdr.conf"
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#endif
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#define FLASH_DUMMY_CYCLES 0x06
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#define FLASH_DUMMY_VALUE 0x06
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const struct flexspi_nor_config_t qspiflash_config = {
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.memConfig = {
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.tag = FLEXSPI_CFG_BLK_TAG,
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.version = FLEXSPI_CFG_BLK_VERSION,
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.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
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.csHoldTime = 3u,
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.csSetupTime = 3u,
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.controllerMiscOption = 0x10,
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.deviceType = kFlexSpiDeviceType_SerialNOR,
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.sflashPadType = kSerialFlash_4Pads,
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.serialClkFreq = kFlexSpiSerialClk_100MHz,
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.sflashA1Size = 16u * 1024u * 1024u,
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.configCmdEnable = 1u,
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.configModeType[0] = kDeviceConfigCmdType_Generic,
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.configCmdSeqs[0] = {
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.seqNum = 1,
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.seqId = 12,
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.reserved = 0,
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},
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.configCmdArgs[0] = (FLASH_DUMMY_VALUE << 3),
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.lookupTable = {
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/* Fast read quad mode - SDR */
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[4 * CMD_LUT_SEQ_IDX_READ + 0] =
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB,
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RADDR_SDR, FLEXSPI_4PAD, 0x18),
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[4 * CMD_LUT_SEQ_IDX_READ + 1] = FLEXSPI_LUT_SEQ(
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DUMMY_SDR, FLEXSPI_4PAD, FLASH_DUMMY_CYCLES,
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READ_SDR, FLEXSPI_4PAD, 0x04),
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/* Read Status LUTs */
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[4 * CMD_LUT_SEQ_IDX_READSTATUS + 0] =
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05,
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READ_SDR, FLEXSPI_1PAD, 0x04),
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/* Write Enable LUTs */
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[4 * CMD_LUT_SEQ_IDX_WRITEENABLE + 0] =
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP,
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FLEXSPI_1PAD, 0x0),
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/* Page Program LUTs */
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[4 * CMD_LUT_SEQ_IDX_WRITE + 0] =
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02,
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RADDR_SDR, FLEXSPI_1PAD, 0x18),
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[4 * CMD_LUT_SEQ_IDX_WRITE + 1] =
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FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP,
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FLEXSPI_1PAD, 0x0),
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},
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},
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.pageSize = 256u,
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.sectorSize = 4u * 1024u,
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.ipcmdSerialClkFreq = 0x1,
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.blockSize = 64u * 1024u,
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.isUniformBlockSize = false,
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};
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#endif /* XIP_BOOT_HEADER_ENABLE */

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