Skip to content

Commit ff9443a

Browse files
VynDragonVynDragon
committed
bflb: attempt to address e24 cores boot failures
Clean up code and add attempts to prevent bl60x and bl70x from failing to boot. Signed-off-by: Camille BAUD <mail@massdriver.space>
1 parent 0d794df commit ff9443a

File tree

10 files changed

+64
-84
lines changed

10 files changed

+64
-84
lines changed

‎soc/bflb/bl60x/Kconfig

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,6 @@ config SOC_SERIES_BL60X
1515
select RISCV
1616
select RISCV_HAS_CLIC
1717
select RISCV_MACHINE_TIMER
18-
select RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING
1918
select RISCV_PRIVILEGED
2019
select RISCV_ISA_RV32I
2120
select RISCV_ISA_EXT_M

‎soc/bflb/bl60x/Kconfig.defconfig

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,9 +5,9 @@
55
if SOC_SERIES_BL60X
66

77
# On BL602 and BL604, not all values work, here is a list of some that work:
8-
# 5000, 1000, 100, 10, 1
8+
# 1000, 100, 10, 1
99
config SYS_CLOCK_TICKS_PER_SEC
10-
default 5000
10+
default 1000
1111

1212
config NUM_IRQS
1313
default 80

‎soc/bflb/bl60x/soc.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,8 @@
2121
#include <hbn_reg.h>
2222
#include <pds_reg.h>
2323

24+
extern void soc_bflb_cache_invalidate(void);
25+
2426
/* Set Embedded Flash Pullup */
2527
static void system_bor_init(void)
2628
{
@@ -51,6 +53,7 @@ void soc_early_init_hook(void)
5153

5254
key = irq_lock();
5355

56+
soc_bflb_cache_invalidate();
5457

5558
/* disable hardware_pullup_pull_down (reg_en_hw_pu_pd = 0) */
5659
tmp = sys_read32(HBN_BASE + HBN_IRQ_MODE_OFFSET);

‎soc/bflb/bl70x/Kconfig

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,6 @@ config SOC_SERIES_BL70X
1414
select RISCV
1515
select RISCV_HAS_CLIC
1616
select RISCV_MACHINE_TIMER
17-
select RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING
1817
select RISCV_PRIVILEGED
1918
select RISCV_ISA_RV32I
2019
select RISCV_ISA_EXT_M

‎soc/bflb/bl70x/Kconfig.defconfig

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,9 +5,9 @@
55
if SOC_SERIES_BL70X
66

77
# On BL702, BL704 and BL706, not all values work, here is a list of some that work:
8-
# 2000, 1000, 100, 10, 1
8+
# 1000, 100, 10, 1
99
config SYS_CLOCK_TICKS_PER_SEC
10-
default 2000
10+
default 1000
1111

1212
config NUM_IRQS
1313
default 80

‎soc/bflb/bl70x/soc.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,8 @@
2020
#include <hbn_reg.h>
2121
#include <pds_reg.h>
2222

23+
extern void soc_bflb_cache_invalidate(void);
24+
2325
/* Set Embedded Flash Pullup */
2426
static void system_bor_init(void)
2527
{
@@ -50,6 +52,7 @@ void soc_early_init_hook(void)
5052

5153
key = irq_lock();
5254

55+
soc_bflb_cache_invalidate();
5356

5457
/* disable hardware_pullup_pull_down (reg_en_hw_pu_pd = 0) */
5558
tmp = sys_read32(HBN_BASE + HBN_IRQ_MODE_OFFSET);

‎soc/bflb/common/CMakeLists.txt

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,5 +8,7 @@ if(CONFIG_SOC_SERIES_BL60X OR CONFIG_SOC_SERIES_BL70X)
88
zephyr_include_directories(e24)
99
zephyr_sources(
1010
e24/soc_irq_privileged.c
11-
e24/intc_clic.S)
11+
e24/intc_clic.S
12+
e24/cache.c
13+
)
1214
endif()

‎soc/bflb/common/e24/cache.c

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,51 @@
1+
/*
2+
* Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#include <zephyr/kernel.h>
8+
9+
#include <bflb_soc.h>
10+
#include <l1c_reg.h>
11+
12+
void __ramfunc soc_bflb_cache_invalidate(void)
13+
{
14+
uint32_t tmp;
15+
16+
tmp = *((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET));
17+
tmp |= 1 << L1C_BYPASS_POS;
18+
tmp &= ~(1 << L1C_CACHEABLE_POS);
19+
tmp &= ~L1C_WAY_DIS_MSK;
20+
tmp &= ~(1 << L1C_CNT_EN_POS);
21+
*((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET)) = tmp;
22+
23+
tmp &= ~(1 << L1C_INVALID_EN_POS);
24+
*((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET)) = tmp;
25+
__asm__ volatile (".rept 4 ; nop ; .endr");
26+
27+
tmp |= (1 << L1C_INVALID_EN_POS);
28+
*((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET)) = tmp;
29+
__asm__ volatile (".rept 4 ; nop ; .endr");
30+
31+
while ((*((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET))
32+
& L1C_INVALID_DONE_MSK) == 0) {
33+
__asm__ volatile (".rept 50 ; nop ; .endr");
34+
}
35+
36+
tmp = *((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET));
37+
tmp |= 1 << L1C_BYPASS_POS;
38+
*((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET)) = tmp;
39+
40+
tmp &= ~(1 << L1C_BYPASS_POS);
41+
tmp |= 1 << L1C_CNT_EN_POS;
42+
*((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET)) = tmp;
43+
44+
tmp &= ~L1C_WAY_DIS_MSK;
45+
*((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET)) = tmp;
46+
47+
tmp |= 1 << L1C_CACHEABLE_POS;
48+
*((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET)) = tmp;
49+
50+
__asm__ volatile (".rept 100 ; nop ; .endr");
51+
}

‎soc/bflb/common/e24/clic.h

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -23,12 +23,4 @@
2323
#define CLIC_INTCFG 0x800
2424
#define CLIC_CFG 0xc00
2525

26-
/* CLIC relative CSR number */
27-
#define CSR_MTVT (0x307)
28-
#define CSR_MNXTI (0x345)
29-
#define CSR_MINTTHRESH (0x347)
30-
#define CSR_MISELECT (0x350)
31-
#define CSR_MIREG (0x351)
32-
#define CSR_MIREG2 (0x352)
33-
3426
#endif /* _SIFIVE_CLIC_H */

‎soc/bflb/common/e24/intc_clic.S

Lines changed: 0 additions & 69 deletions
Original file line numberDiff line numberDiff line change
@@ -9,19 +9,6 @@
99
*/
1010

1111
#include <zephyr/arch/cpu.h>
12-
#include "clic.h"
13-
14-
15-
/* register-wide load/store based on lw/sw (XLEN = 32) */
16-
17-
.macro lr, rd, mem
18-
lw \rd, \mem
19-
.endm
20-
21-
.macro sr, rs, mem
22-
sw \rs, \mem
23-
.endm
24-
2512

2613
GTEXT(__soc_handle_irq)
2714
/*
@@ -33,59 +20,3 @@ GTEXT(__soc_handle_irq)
3320
*/
3421
SECTION_FUNC(exception.other, __soc_handle_irq)
3522
ret
36-
37-
GTEXT(__soc_handle_all_irqs)
38-
39-
#ifdef CONFIG_TRACING
40-
/* imports */
41-
GTEXT(sys_trace_isr_enter)
42-
GTEXT(sys_trace_isr_exit)
43-
#endif
44-
45-
/*
46-
* This function services and clears all pending interrupts for an CLIC in non-vectored mode.
47-
*/
48-
SECTION_FUNC(exception.other, __soc_handle_all_irqs)
49-
addi sp, sp, -16
50-
sr ra, 0(sp)
51-
52-
/* Read and clear mnxti to get highest current interrupt and enable interrupts. Will return
53-
* original interrupt if no others appear. */
54-
csrrci a0, CSR_MNXTI, MSTATUS_IEN
55-
beqz a0, irq_done /* Check if original interrupt vanished. */
56-
57-
irq_loop:
58-
59-
#ifdef CONFIG_TRACING_ISR
60-
call sys_trace_isr_enter
61-
#endif
62-
63-
/* Call corresponding registered function in _sw_isr_table. a0 is offset in pointer with
64-
* the mtvt, sw irq table is 2-pointer wide -> shift by one. */
65-
csrr t0, CSR_MTVT
66-
sub a0, a0, t0
67-
la t0, _sw_isr_table
68-
slli a0, a0, (1)
69-
add t0, t0, a0
70-
71-
/* Load argument in a0 register */
72-
lr a0, 0(t0)
73-
74-
/* Load ISR function address in register t1 */
75-
lr t1, RV_REGSIZE(t0)
76-
77-
/* Call ISR function */
78-
jalr ra, t1, 0
79-
80-
#ifdef CONFIG_TRACING_ISR
81-
call sys_trace_isr_exit
82-
#endif
83-
84-
/* Read and clear mnxti to get highest current interrupt and enable interrupts. */
85-
csrrci a0, CSR_MNXTI, MSTATUS_IEN
86-
bnez a0, irq_loop
87-
88-
irq_done:
89-
lr ra, 0(sp)
90-
addi sp, sp, 16
91-
ret

0 commit comments

Comments
 (0)