diff --git a/boards/phytec/phyboard_atlas/CMakeLists.txt b/boards/phytec/phyboard_atlas/CMakeLists.txt new file mode 100644 index 000000000000..e06640f80bd0 --- /dev/null +++ b/boards/phytec/phyboard_atlas/CMakeLists.txt @@ -0,0 +1,32 @@ +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_library() + set(RT1170_BOARD_NAME "evkmimxrt1170") + set(RT1170_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/${RT1170_BOARD_NAME}") + if(CONFIG_BOOT_FLEXSPI_NOR) + # Include flash configuration block for RT1170 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN12238 for more information. + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_library_sources(flexspi_nor_config.c) + endif() + if(CONFIG_EXTERNAL_MEM_CONFIG_DATA) + # Include external memory configuration data block for RT1170 EVK from NXP's HAL. + # This configuration block may need modification if another SDRAM chip + # is used on your custom board. + zephyr_compile_definitions(XIP_BOOT_HEADER_XMCD_ENABLE=1) + zephyr_library_sources(${RT1170_BOARD_DIR}/xmcd/xmcd.c) + else() + if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) + message(WARNING "You are using SDRAM as RAM but no external memory" + "configuration data (XMCD) is included. This configuration may not boot") + endif() + endif() +endif() + +if(CONFIG_MCUX_GPT_TIMER) + message(WARNING "You appear to be using the GPT hardware timer. " + "This timer will enable lower power modes, but at the cost of reduced " + "hardware timer resolution") +endif() diff --git a/boards/phytec/phyboard_atlas/Kconfig.defconfig b/boards/phytec/phyboard_atlas/Kconfig.defconfig new file mode 100644 index 000000000000..f23ccc915d60 --- /dev/null +++ b/boards/phytec/phyboard_atlas/Kconfig.defconfig @@ -0,0 +1,44 @@ +# PHYBOARD-ATLAS + +# Copyright (c) 2025 PHYTEC America, LLC +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PHYBOARD_ATLAS + +# Only use DCD when booting primary core (M7) +config EXTERNAL_MEM_CONFIG_DATA + default y if CPU_CORTEX_M7 + +config NXP_IMX_EXTERNAL_SDRAM + default y if CPU_CORTEX_M7 + +if SECOND_CORE_MCUX && CPU_CORTEX_M4 + +config BUILD_OUTPUT_INFO_HEADER + default y + +DT_CHOSEN_IMAGE_M4 = nxp,m4-partition + +# Adjust the offset of the output image if building for RT11xx SOC +config BUILD_OUTPUT_ADJUST_LMA + default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_M4)) + \ + $(dt_node_reg_addr_hex,/soc/spi@400cc000,1)) - \ + $(dt_node_reg_addr_hex,/soc/ocram@20200000)" + +endif # SECOND_CORE_MCUX && CPU_CORTEX_M4 + +if NETWORKING + +config NET_L2_ETHERNET + default y if CPU_CORTEX_M7 # No cache memory support is required for driver + +endif # NETWORKING + +if DISK_DRIVERS + +config IMX_USDHC_DAT3_PWR_TOGGLE + default y + +endif # DISK_DRIVERS + +endif # BOARD_PHYBOARD_ATLAS diff --git a/boards/phytec/phyboard_atlas/Kconfig.phyboard_atlas b/boards/phytec/phyboard_atlas/Kconfig.phyboard_atlas new file mode 100644 index 000000000000..7d90a5476d27 --- /dev/null +++ b/boards/phytec/phyboard_atlas/Kconfig.phyboard_atlas @@ -0,0 +1,7 @@ +# Copyright 2025 PHYTEC America, LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PHYBOARD_ATLAS + select SOC_MIMXRT1176_CM7 if BOARD_PHYBOARD_ATLAS_MIMXRT1176_CM7 + select SOC_MIMXRT1176_CM4 if BOARD_PHYBOARD_ATLAS_MIMXRT1176_CM4 + select SOC_PART_NUMBER_MIMXRT1176DVMAA diff --git a/boards/phytec/phyboard_atlas/board.cmake b/boards/phytec/phyboard_atlas/board.cmake new file mode 100644 index 000000000000..a970fdb67e34 --- /dev/null +++ b/boards/phytec/phyboard_atlas/board.cmake @@ -0,0 +1,18 @@ +if(CONFIG_SOC_MIMXRT1176_CM7 OR CONFIG_SECOND_CORE_MCUX) + board_runner_args(pyocd "--target=mimxrt1170_cm7") + board_runner_args(jlink "--device=MIMXRT1176xxxA_M7" "--reset-after-load") + + board_runner_args(linkserver "--device=MIMXRT1176xxxxx:MIMXRT1170-EVK") + board_runner_args(linkserver "--core=cm7") +elseif(CONFIG_SOC_MIMXRT1176_CM4) + board_runner_args(pyocd "--target=mimxrt1170_cm4") + # Note: Please use JLINK above V7.50 (Only support run cm4 image when debugging due to default boot core on board is cm7 core) + board_runner_args(jlink "--device=MIMXRT1176xxxA_M4") + + board_runner_args(linkserver "--device=MIMXRT1176xxxxx:MIMXRT1170-EVK") + board_runner_args(linkserver "--core=cm4") +endif() + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) diff --git a/boards/phytec/phyboard_atlas/board.yml b/boards/phytec/phyboard_atlas/board.yml new file mode 100644 index 000000000000..acde92130990 --- /dev/null +++ b/boards/phytec/phyboard_atlas/board.yml @@ -0,0 +1,6 @@ +board: + name: phyboard_atlas + full_name: phyBOARD-Atlas i.MX RT1170 + vendor: phytec + socs: + - name: mimxrt1176 diff --git a/boards/phytec/phyboard_atlas/doc/img/phyboard_atlas.webp b/boards/phytec/phyboard_atlas/doc/img/phyboard_atlas.webp new file mode 100644 index 000000000000..54954bca017e Binary files /dev/null and b/boards/phytec/phyboard_atlas/doc/img/phyboard_atlas.webp differ diff --git a/boards/phytec/phyboard_atlas/doc/index.rst b/boards/phytec/phyboard_atlas/doc/index.rst new file mode 100644 index 000000000000..955836a29147 --- /dev/null +++ b/boards/phytec/phyboard_atlas/doc/index.rst @@ -0,0 +1,388 @@ +.. zephyr:board:: phyboard_atlas + +Overview +******** + +PHYTEC phyBOARD-Atlas i.MX RT1170 board features phyCORE-i.MX RT1170 System on +Module. The phyCORE-i.MX RT1170 module is based on the NXP dual core i.MX RT1170 +which runs on the Cortex-M7 core at 1 GHz and on the Cortex-M4 at 400 MHz. + +Hardware +******** + +- MIMXRT1176DVMAA MCU + + - 1GHz Cortex-M7 & 400Mhz Cortex-M4 + - 2MB SRAM with 512KB of TCM for Cortex-M7 and 256KB of TCM for Cortex-M4 + +- Memory + + - 512 Mbit SDRAM + - 128 Mbit QSPI Flash + - 512 Mbit Octal Flash + +- Interfaces + + - MicroSD: 1x microSD Card slot + - USB: 2x USB 2.0 OTG + - Ethernet: 1x 10/100/1000BASE-T & 1x 10/100BASE-T (RJ45) + - Expansion: 1x M.2 Connector + - Display: 1x MIPI-DSI + - Camera: 1x MIPI CSI + - Audio: Standard Audio Interface + - Serial: 1x RS232 (2x5 pin header) + 1x RS485 + - UART: 1x via Expansion Interface + - CAN: 1x CAN (2x5 pin header) + - LED: 1x RGB User LED + - Expansion Interface: 60-pin + - Security: OPTIGA™ TPM SLB 9670 TPM 2.0 + - Power Input: USB-C 5V/3A + +- Debug + + - Micro USB serial debug interface + - JTAG: via Expansion Interface + +For more information about phyCORE-i.MX RT1170 & phyBOARD-Atlas i.MX RT1170 +board, see these references: + +- `phyCORE-i.MX RT1170 Product Page`_ +- `phyBOARD-Atlas i.MX RT1170 Product Page`_ + +External Memory +=============== + +This platform has the following external memories: + ++----------------------+------------+-------------------------------------+ +| Device | Controller | Status | ++======================+============+=====================================+ +| MT48LC16M16A2B4-7EIT | SEMC | Enabled via device configuration | +| SDRAM | | data (DCD) block, which sets up | +| | | the SEMC at boot time | ++----------------------+------------+-------------------------------------+ +| MX25U12832FM2I02 | FLEXSPI | Enabled via flash configuration | +| QSPI flash | | block (FCB), which sets up the | +| | | FLEXSPI at boot time. | ++----------------------+------------+-------------------------------------+ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and I/Os +==================== + +The MIMXRT1170 SoC has six pairs of pinmux/gpio controllers. + ++---------------------------+----------------------+-------------------------------+ +| Name | Function | Usage | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_35 | GPIO | User button | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SNVS_08 | GPIO | Red LED (SOM) | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SNVS_09 | GPIO | Green LED (SOM) | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_14 | GPIO | Red LED (Carrier Board) | ++---------------------------+----------------------+-------------------------------+ +| GPIO_LPSR_13 | GPIO | Green LED (Carrier Board) | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_18 | LPI2C2_SCL | EEPROM | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_19 | LPI2C2_SDA | EEPROM | ++---------------------------+----------------------+-------------------------------+ +| GPIO_LPSR_08 | LPI2C5_SCL | Accelerometer, CODEC, Display | ++---------------------------+----------------------+-------------------------------+ +| GPIO_LPSR_09 | LPI2C5_SDA | Accelerometer, CODEC, Display | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_24 | LPUART1_TX | UART Console (CM7) | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_25 | LPUART1_RX | UART Console (CM7) | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_28 | LPUART5_TX | UART | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_29 | LPUART5_RX | UART | ++---------------------------+----------------------+-------------------------------+ +| GPIO_EMC_B1_40 | LPUART6_TX | UART Console (CM4) | ++---------------------------+----------------------+-------------------------------+ +| GPIO_EMC_B1_41 | LPUART6_RX | UART Console (CM4) | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_00 | CTP_INT | Display | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_01 | CTP_RST_B | Display | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B2_05 | PWR_EN | Display | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_30 | Backlight_CTL | Display | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_32 | ENET_MDC | Ethernet | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_33 | ENET_MDIO | Ethernet | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B2_02 | ENET_TX_DATA00 | Ethernet | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B2_03 | ENET_TX_DATA01 | Ethernet | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B2_04 | ENET_TX_EN | Ethernet | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B2_05 | ENET_TX_CLK | Ethernet | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B2_06 | ENET_RX_DATA00 | Ethernet | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B2_07 | ENET_RX_DATA01 | Ethernet | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B2_08 | ENET_RX_EN | Ethernet | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B2_09 | ENET_RX_ER | Ethernet | ++---------------------------+----------------------+-------------------------------+ +| GPIO_EMC_B2_19 | ENET_RGMII_MDC | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_EMC_B2_20 | ENET_RGMII_MDIO | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B1_09 | ENET_RGMII_TX_DATA00 | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B1_08 | ENET_RGMII_TX_DATA01 | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B1_07 | ENET_RGMII_TX_DATA02 | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B1_06 | ENET_RGMII_TX_DATA03 | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B1_10 | ENET_RGMII_TX_EN | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B1_11 | ENET_RGMII_TX_CLK | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B1_02 | ENET_RGMII_RX_DATA00 | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B1_03 | ENET_RGMII_RX_DATA01 | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B1_04 | ENET_RGMII_RX_DATA02 | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B1_05 | ENET_RGMII_RX_DATA03 | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B1_00 | ENET_RGMII_RX_EN | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_DISP_B1_01 | ENET_RGMII_RX_CLK | Ethernet 1G | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_02 | LPUART8_TX | RS-232 | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_03 | LPUART8_RX | RS-232 | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_04 | LPUART8_CTS | RS-232 | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_05 | LPUART8_RTS | RS-232 | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SD_B2_05 | FLEXSPI1_DQS | Flash Programming | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SD_B2_06 | FLEXSPI1_SS0 | Flash Programming | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SD_B2_07 | FLEXSPI1_SCLK | Flash Programming | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SD_B2_08 | FLEXSPI1_DATA00 | Flash Programming | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SD_B2_09 | FLEXSPI1_DATA01 | Flash Programming | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SD_B2_10 | FLEXSPI1_DATA02 | Flash Programming | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SD_B2_11 | FLEXSPI1_DATA03 | Flash Programming | ++---------------------------+----------------------+-------------------------------+ +| GPIO_LPSR_00 | CAN3_TX | FlexCAN | ++---------------------------+----------------------+-------------------------------+ +| GPIO_LPSR_01 | CAN3_RX | FlexCAN | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_17_SAI1_MCLK | SAI_MCLK | CODEC/SAI | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_20_SAI1_RX_DATA00 | SAI1_RX_DATA00 | CODEC/SAI | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_21_SAI1_TX_DATA00 | SAI1_TX_DATA00 | CODEC/SAI | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_22_SAI1_TX_BCLK | SAI1_TX_BCLK | CODEC/SAI | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_23_SAI1_TX_SYNC | SAI1_TX_SYNC | CODEC/SAI | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SD_B1_00 | USDHC1_CMD | SDHC | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SD_B1_01 | USDHC1_CLK | SDHC | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SD_B1_02 | USDHC1_DATA0 | SDHC | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SD_B1_03 | USDHC1_DATA1 | SDHC | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SD_B1_04 | USDHC1_DATA2 | SDHC | ++---------------------------+----------------------+-------------------------------+ +| GPIO_SD_B1_05 | USDHC1_DATA3 | SDHC | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_09 | USB_OTG1_ID | USB | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_10 | USB_OTG1_PWR | USB | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_11 | USB_OTG1_OC | USB | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_08 | USB_OTG2_ID | USB | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_07 | USB_OTG2_PWR | USB | ++---------------------------+----------------------+-------------------------------+ +| GPIO_AD_06 | USB_OTG2_OC | USB | ++---------------------------+----------------------+-------------------------------+ + +Dual Core samples +***************** + ++-----------+------------------+------------------+ +| Core | Boot Address | Comment | ++===========+==================+==================+ +| Cortex M7 | 0x30000000[630K] | primary core | ++-----------+------------------+------------------+ +| Cortex M4 | 0x20020000[96k] | boots from OCRAM | ++-----------+------------------+------------------+ + ++----------+------------------+-----------------------+ +| Memory | Address[Size] | Comment | ++==========+==================+=======================+ +| flexspi1 | 0x30000000[16M] | Cortex M7 flash | ++----------+------------------+-----------------------+ +| sdram0 | 0x80030000[64M] | Cortex M7 ram | ++----------+------------------+-----------------------+ +| ocram | 0x20020000[512K] | Cortex M4 "flash" | ++----------+------------------+-----------------------+ +| sram1 | 0x20000000[128K] | Cortex M4 ram | ++----------+------------------+-----------------------+ +| ocram2 | 0x200C0000[512K] | Mailbox/shared memory | ++----------+------------------+-----------------------+ + +Only the first 16K of ocram2 has the correct MPU region attributes set to be +used as shared memory + +System Clock +============ + +The MIMXRT1170 SoC is configured to use SysTick as the system clock source, +running at 996MHz. When targeting the M4 core, SysTick will also be used, +running at 400MHz + +When power management is enabled, the 32 KHz low frequency +oscillator on the board will be used as a source for the GPT timer to +generate a system clock. This clock enables lower power states, at the +cost of reduced resolution + +Serial Port +=========== + +The MIMXRT1170 SoC has 12 UARTs. ``LPUART1`` is configured for the console for +the CM7 and ``LPUART6`` is configured for the console of the CM4. ``LPUART8`` is +configured for RS-232. Remaining are not used. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Building a Dual-Core Image +========================== +Dual core samples load the M4 core image from flash into the shared ``ocram`` +region. The M7 core then sets the M4 boot address to this region. The only +sample currently enabled for dual core builds is the ``openamp`` sample. +To flash a dual core sample, the M4 image must be flashed first, so that it is +written to flash. Then, the M7 image must be flashed. The openamp sysbuild +sample will do this automatically by setting the image order. + +The secondary core can be debugged normally in single core builds +(where the target is ``phyboard_atlas/mimxrt1176/cm4``). For dual core builds, the +secondary core should be placed into a loop, then a debugger can be attached +(see `AN13264`_, section 4.2.3 for more information) + +Launching Images Targeting M4 Core +================================== +If building targeting the M4 core, the M7 core must first run code to launch +the M4 image, by copying it into the ``ocram`` region then kicking off the M4 +core. When building using sysbuild targeting the M4 core, a minimal "launcher" +image will be built and flashed to the M7 core, which loads and kicks off +the M4 core. Therefore when developing an application intended to run +standalone on the M4 core, it is recommended to build with sysbuild, like +so: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: phyboard_atlas/mimxrt1176/cm4 + :west-args: --sysbuild + :goals: flash + +If desired, this behavior can be disabled by building with +``-DSB_CONFIG_SECOND_CORE_MCUX_LAUNCHER=n`` + +Configuring a Debug Probe +========================= + +X18 is a standard 10-pin ARM debug connector, which can be used to connect +an external CMSIS-DAP (e.g., NXP MCU-Link) or a J-Link debug adapter. + +Using J-Link +------------ + +JLink is the default runner for this board. Install the +:ref:`jlink-debug-host-tools` and make sure they are in your search path. + +Configuring a Console +===================== + +We will use the on-board FTDI UART-to-USB IC that converts the two internal +UARTs to USB (X15). + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: phyboard_atlas/mimxrt1176/cm7 + :goals: flash + +You should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v4.1.0-xxxx-xxxxxxxxxxxxx ***** + Hello World! phyboard_atlas/mimxrt1176/cm7 + +Debugging +========= + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: phyboard_atlas/mimxrt1176/cm7 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v4.1.0-xxxx-xxxxxxxxxxxxx ***** + Hello World! phyboard_atlas/mimxrt1176/cm7 + +References +********** + +.. target-notes:: + +.. _phyCORE-i.MX RT1170 Product Page: + https://www.phytec.com/product/phycore-rt1170 + +.. _phyBOARD-Atlas i.MX RT1170 Product Page: + https://www.phytec.com/product/phyboard-rt1170-development-kit/ + +.. _AN13264: + https://www.nxp.com/docs/en/application-note/AN13264.pdf diff --git a/boards/phytec/phyboard_atlas/flexspi_nor_config.c b/boards/phytec/phyboard_atlas/flexspi_nor_config.c new file mode 100644 index 000000000000..aa57c9061949 --- /dev/null +++ b/boards/phytec/phyboard_atlas/flexspi_nor_config.c @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2025 PHYTEC America, LLC + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +#define FLASH_DUMMY_CYCLES 0x06 +#define FLASH_DUMMY_VALUE 0x06 + +const struct flexspi_nor_config_t qspiflash_config = { + .memConfig = { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .controllerMiscOption = 0x10, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_100MHz, + .sflashA1Size = 16u * 1024u * 1024u, + .configCmdEnable = 1u, + .configModeType[0] = kDeviceConfigCmdType_Generic, + .configCmdSeqs[0] = { + .seqNum = 1, + .seqId = 12, + .reserved = 0, + }, + .configCmdArgs[0] = (FLASH_DUMMY_VALUE << 3), + .lookupTable = { + /* Fast read quad mode - SDR */ + [4 * CMD_LUT_SEQ_IDX_READ + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, + RADDR_SDR, FLEXSPI_4PAD, 0x18), + [4 * CMD_LUT_SEQ_IDX_READ + 1] = FLEXSPI_LUT_SEQ( + DUMMY_SDR, FLEXSPI_4PAD, FLASH_DUMMY_CYCLES, + READ_SDR, FLEXSPI_4PAD, 0x04), + + /* Read Status LUTs */ + [4 * CMD_LUT_SEQ_IDX_READSTATUS + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, + READ_SDR, FLEXSPI_1PAD, 0x04), + + /* Write Enable LUTs */ + [4 * CMD_LUT_SEQ_IDX_WRITEENABLE + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, + FLEXSPI_1PAD, 0x0), + + /* Page Program LUTs */ + [4 * CMD_LUT_SEQ_IDX_WRITE + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, + RADDR_SDR, FLEXSPI_1PAD, 0x18), + [4 * CMD_LUT_SEQ_IDX_WRITE + 1] = + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP, + FLEXSPI_1PAD, 0x0), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = 0x1, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/boards/phytec/phyboard_atlas/phyboard_atlas-pinctrl.dtsi b/boards/phytec/phyboard_atlas/phyboard_atlas-pinctrl.dtsi new file mode 100644 index 000000000000..41039b90f96a --- /dev/null +++ b/boards/phytec/phyboard_atlas/phyboard_atlas-pinctrl.dtsi @@ -0,0 +1,275 @@ +/* + * Copyright (c) 2025 PHYTEC America LLC + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + pinmux_enet: pinmux_enet { + group0 { + pinmux = <&iomuxc_gpio_disp_b2_08_enet_rx_en>, + <&iomuxc_gpio_disp_b2_09_enet_rx_er>; + drive-strength = "high"; + bias-pull-down; + slew-rate = "fast"; + }; + + group1 { + pinmux = <&iomuxc_gpio_disp_b2_06_enet_rdata00>, + <&iomuxc_gpio_disp_b2_07_enet_rdata01>; + drive-strength = "high"; + bias-pull-down; + slew-rate = "fast"; + input-enable; + }; + + group2 { + pinmux = <&iomuxc_gpio_disp_b2_02_enet_tdata00>, + <&iomuxc_gpio_disp_b2_03_enet_tdata01>, + <&iomuxc_gpio_disp_b2_04_enet_tx_en>; + drive-strength = "high"; + slew-rate = "fast"; + }; + + group3 { + pinmux = <&iomuxc_gpio_disp_b2_05_enet_ref_clk>; + drive-strength = "high"; + slew-rate = "slow"; + input-enable; + }; + }; + + pinmux_enet_mdio: pinmux_enet_mdio { + group0 { + pinmux = <&iomuxc_gpio_ad_32_enet_mdc>, + <&iomuxc_gpio_ad_33_enet_mdio>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_lcdif: pinmux_lcdif { + group0 { + pinmux = <&iomuxc_gpio_ad_30_gpio9_io29>, + <&iomuxc_gpio_ad_31_gpio9_io30>; + drive-strength = "high"; + bias-pull-down; + slew-rate = "fast"; + }; + + group1 { + pinmux = <&iomuxc_gpio_disp_b2_15_gpio11_io16>; + drive-strength = "high"; + bias-pull-up; + slew-rate = "fast"; + }; + }; + + pinmux_lpi2c1: pinmux_lpi2c1 { + group0 { + pinmux = <&iomuxc_gpio_ad_08_lpi2c1_scl>, + <&iomuxc_gpio_ad_09_lpi2c1_sda>; + drive-strength = "normal"; + drive-open-drain; + slew-rate = "fast"; + input-enable; + }; + }; + + pinmux_lpi2c5: pinmux_lpi2c5 { + group0 { + pinmux = <&iomuxc_lpsr_gpio_lpsr_08_lpi2c5_sda>, + <&iomuxc_lpsr_gpio_lpsr_09_lpi2c5_scl>; + drive-strength = "normal"; + drive-open-drain; + slew-rate = "fast"; + input-enable; + }; + }; + + pinmux_lpspi1: pinmux_lpspi1 { + group0 { + pinmux = <&iomuxc_gpio_ad_29_lpspi1_pcs0>, + <&iomuxc_gpio_ad_28_lpspi1_sck>, + <&iomuxc_gpio_ad_31_lpspi1_sdi>, + <&iomuxc_gpio_ad_30_lpspi1_sdo>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_lpspi5: pinmux_lpspi5 { + group0 { + pinmux = <&iomuxc_lpsr_gpio_lpsr_03_lpspi5_pcs0>, + <&iomuxc_lpsr_gpio_lpsr_06_lpspi5_pcs1>, + <&iomuxc_lpsr_gpio_lpsr_07_lpspi5_pcs2>, + <&iomuxc_lpsr_gpio_lpsr_02_lpspi5_sck>, + <&iomuxc_lpsr_gpio_lpsr_05_lpspi5_sdi>, + <&iomuxc_lpsr_gpio_lpsr_04_lpspi5_sdo>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_lpuart1: pinmux_lpuart1 { + group0 { + pinmux = <&iomuxc_gpio_ad_25_lpuart1_rx>, + <&iomuxc_gpio_ad_24_lpuart1_tx>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_lpuart1_sleep: pinmux_lpuart1_sleep { + group0 { + pinmux = <&iomuxc_gpio_ad_25_gpio_mux3_io24>; + drive-strength = "high"; + bias-pull-up; + slew-rate = "fast"; + }; + + group1 { + pinmux = <&iomuxc_gpio_ad_24_lpuart1_tx>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_lpuart5: pinmux_lpuart5 { + group0 { + pinmux = <&iomuxc_gpio_ad_29_lpuart5_rx>, + <&iomuxc_gpio_ad_28_lpuart5_tx>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_lpuart5_sleep: pinmux_lpuart5_sleep { + group0 { + pinmux = <&iomuxc_gpio_ad_29_gpio_mux3_io28>; + drive-strength = "high"; + bias-pull-up; + slew-rate = "fast"; + }; + + group1 { + pinmux = <&iomuxc_gpio_ad_28_lpuart5_tx>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_lpuart6: pinmux_lpuart6 { + group0 { + pinmux = <&iomuxc_gpio_emc_b1_41_lpuart6_rx>, + <&iomuxc_gpio_emc_b1_40_lpuart6_tx>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_lpuart6_sleep: pinmux_lpuart6_sleep { + group0 { + pinmux = <&iomuxc_gpio_emc_b1_41_gpio_mux2_io09>; + drive-strength = "high"; + bias-pull-up; + slew-rate = "fast"; + }; + + group1 { + pinmux = <&iomuxc_gpio_emc_b1_40_lpuart6_tx>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_lpuart8: pinmux_lpuart8 { + group0 { + pinmux = <&iomuxc_gpio_ad_03_lpuart8_rx>, + <&iomuxc_gpio_ad_02_lpuart8_tx>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_lpuart8_sleep: pinmux_lpuart8_sleep { + group0 { + pinmux = <&iomuxc_gpio_ad_03_gpio9_io02>; + drive-strength = "high"; + bias-pull-up; + slew-rate = "fast"; + }; + + group1 { + pinmux = <&iomuxc_gpio_ad_02_lpuart8_tx>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_lpuart8_flowcontrol: pinmux_lpuart8_flowcontrol { + group0 { + pinmux = <&iomuxc_gpio_ad_03_lpuart8_rx>, + <&iomuxc_gpio_ad_02_lpuart8_tx>, + <&iomuxc_gpio_ad_04_lpuart8_cts_b>, + <&iomuxc_gpio_ad_05_lpuart8_rts_b>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_flexcan3: pinmux_flexcan3 { + group0 { + pinmux = <&iomuxc_lpsr_gpio_lpsr_01_can3_rx>, + <&iomuxc_lpsr_gpio_lpsr_00_can3_tx>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_sai1: pinmux_sai1 { + group0 { + pinmux = <&iomuxc_gpio_ad_17_sai1_mclk>, + <&iomuxc_gpio_ad_20_sai1_rx_data00>, + <&iomuxc_gpio_ad_21_sai1_tx_data00>, + <&iomuxc_gpio_ad_22_sai1_tx_bclk>, + <&iomuxc_gpio_ad_23_sai1_tx_sync>; + drive-strength = "high"; + slew-rate = "fast"; + input-enable; + }; + }; + + pinmux_usdhc1: pinmux_usdhc1 { + group0 { + pinmux = <&iomuxc_gpio_sd_b1_00_usdhc1_cmd>, + <&iomuxc_gpio_sd_b1_01_usdhc1_clk>, + <&iomuxc_gpio_sd_b1_02_usdhc1_data0>, + <&iomuxc_gpio_sd_b1_03_usdhc1_data1>, + <&iomuxc_gpio_sd_b1_04_usdhc1_data2>, + <&iomuxc_gpio_sd_b1_05_usdhc1_data3>; + bias-pull-up; + input-enable; + }; + }; + + /* removes pull on dat3 for card detect */ + pinmux_usdhc1_dat3_nopull: pinmux_usdhc1_dat3_nopull { + group0 { + pinmux = <&iomuxc_gpio_sd_b1_05_usdhc1_data3>; + bias-disable; + input-enable; + }; + + group1 { + pinmux = <&iomuxc_gpio_sd_b1_00_usdhc1_cmd>, + <&iomuxc_gpio_sd_b1_01_usdhc1_clk>, + <&iomuxc_gpio_sd_b1_02_usdhc1_data0>, + <&iomuxc_gpio_sd_b1_03_usdhc1_data1>, + <&iomuxc_gpio_sd_b1_04_usdhc1_data2>; + bias-pull-up; + input-enable; + }; + }; +}; diff --git a/boards/phytec/phyboard_atlas/phyboard_atlas.dtsi b/boards/phytec/phyboard_atlas/phyboard_atlas.dtsi new file mode 100644 index 000000000000..32cfeffe5fe5 --- /dev/null +++ b/boards/phytec/phyboard_atlas/phyboard_atlas.dtsi @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2025 PHYTEC America LLC + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "phyboard_atlas-pinctrl.dtsi" +#include + +/ { + aliases { + accel0 = &icm40627; + eeprom-0 = &eeprom0; + led0 = &som_green_led; + led1 = &som_red_led; + led3 = &board_red_led; + led4 = &board_green_led; + sdhc0 = &usdhc1; + sdram0 = &sdram0; + sw0 = &user_button; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button: button-1 { + label = "User Button"; + gpios = <&gpio10 2 GPIO_ACTIVE_HIGH>; + zephyr,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + board_red_led: led-3 { + label = "Red LED1 D4"; + gpios = <&gpio9 13 GPIO_ACTIVE_HIGH>; + }; + + board_green_led: led-4 { + label = "Green LED2 D11"; + gpios = <&gpio12 13 GPIO_ACTIVE_HIGH>; + }; + }; + + expansion_header: connector { + compatible = "gpio-nexus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <11 0 &gpio4 1 0>, /* Pin 11, GPIO_AD_34 */ + <27 0 &gpio3 25 0>, /* Pin 27, EXP_AD_26 */ + <29 0 &gpio3 26 0>, /* Pin 29, EXP_AD_27 */ + <31 0 &gpio5 1 0>, /* Pin 31, GPIO_DISP_B2_00 */ + <33 0 &gpio13 3 0>, /* Pin 33, GPIO_SNVS_00 */ + <35 0 &gpio13 4 0>, /* Pin 35, GPIO_SNVS_01 */ + <36 0 &gpio13 5 0>, /* Pin 36, GPIO_SNVS_02 */ + <37 0 &gpio13 6 0>, /* Pin 37, GPIO_SNVS_03 */ + <38 0 &gpio13 7 1>, /* Pin 38, GPIO_SNVS_04 */ + <40 0 &gpio13 8 1>; /* Pin 40, GPIO_SNVS_05 */ + }; + + transceiver0: can-phy0 { + compatible = "can-transceiver-gpio"; + standby-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; +}; + +&enet_mac { + status = "okay"; + pinctrl-0 = <&pinmux_enet>; + pinctrl-names = "default"; + phy-handle = <&phy>; + phy-connection-type = "rmii"; + zephyr,random-mac-address; +}; + +&enet_mdio { + status = "okay"; + pinctrl-0 = <&pinmux_enet_mdio>; + pinctrl-names = "default"; + + phy: phy@1 { + compatible = "microchip,ksz8081"; + reg = <1>; + status = "okay"; + microchip,interface-type = "rmii"; + }; +}; + +&enet_ptp_clock { + status = "okay"; +}; + +&flexcan3 { + pinctrl-0 = <&pinmux_flexcan3>; + pinctrl-names = "default"; +}; + +&lcdif { + pinctrl-0 = <&pinmux_lcdif>; + pinctrl-names = "default"; +}; + +&lpi2c1 { + pinctrl-0 =<&pinmux_lpi2c1>; + pinctrl-names = "default"; +}; + +&lpi2c5 { + pinctrl-0 =<&pinmux_lpi2c5>; + pinctrl-names = "default"; + status = "okay"; + + icm40627: icm40627@69 { + compatible = "invensense,icm40627"; + reg = <0x69>; + status = "okay"; + accel-hz = <1000>; + accel-fs = <16>; + gyro-hz = <1000>; + gyro-fs = <2000>; + int-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>, + <&gpio3 26 GPIO_ACTIVE_HIGH>; + }; + + audio_codec: tlv320aic3110@18 { + compatible = "ti,tlv320aic3110"; + reg = <0x18>; + status = "okay"; + clocks = <&ccm IMX_CCM_SAI1_CLK 0x2004 4>; + clock-names = "mclk"; + }; +}; + +&lpspi1 { + pinctrl-0 = <&pinmux_lpspi1>; + pinctrl-names = "default"; +}; + +&lpspi5 { + pinctrl-0 = <&pinmux_lpspi5>; + pinctrl-names = "default"; +}; + +&lpuart1 { + pinctrl-0 = <&pinmux_lpuart1>; + pinctrl-1 = <&pinmux_lpuart1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&lpuart5 { + pinctrl-0 = <&pinmux_lpuart5>; + pinctrl-1 = <&pinmux_lpuart5_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&lpuart6 { + pinctrl-0 = <&pinmux_lpuart6>; + pinctrl-1 = <&pinmux_lpuart6_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&lpuart8 { + pinctrl-0 = <&pinmux_lpuart8_flowcontrol>; + pinctrl-1 = <&pinmux_lpuart8_sleep>; + pinctrl-names = "default", "sleep"; + hw-flow-control; +}; + +&sai1 { + pinctrl-0 = <&pinmux_sai1>; + pinctrl-names = "default"; +}; + +&usdhc1 { + pinctrl-0 = <&pinmux_usdhc1>; + pinctrl-1 = <&pinmux_usdhc1_dat3_nopull>; + pinctrl-names = "default", "nopull"; +}; diff --git a/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm4.dts b/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm4.dts new file mode 100644 index 000000000000..5d1d38ae339a --- /dev/null +++ b/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm4.dts @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2025 PHYTEC America LLC + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "phyboard_atlas.dtsi" + +/ { + model = "PHYTEC phyBOARD-Atlas i.MX RT1170 CM4"; + compatible = "phytec,phyboard_atlas"; + + chosen { + zephyr,console = &lpuart6; + zephyr,shell-uart = &lpuart6; + }; +}; + +&user_button { + status = "okay"; +}; + +&board_green_led { + status = "okay"; +}; + +&board_red_led { + status = "okay"; +}; + +&lpi2c1 { + status = "okay"; +}; + +&lpuart6 { + status = "okay"; + current-speed = <115200>; +}; + +&sai1 { + status = "okay"; +}; diff --git a/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm4.yaml b/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm4.yaml new file mode 100644 index 000000000000..d7fda563cddf --- /dev/null +++ b/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm4.yaml @@ -0,0 +1,22 @@ +# Copyright (c) 2025 PHYTEC America LLC +# SPDX-License-Identifier: Apache-2.0 + +identifier: phyboard_atlas/mimxrt1176/cm4 +name: PHYTEC phyBOARD-Atlas i.MX RT1170 CM4 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 128 +flash: 128 +supported: + - dac + - dma + - gpio + - i2c + - sai + - spi + - uart +vendor: phytec diff --git a/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm4_defconfig b/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm4_defconfig new file mode 100644 index 000000000000..b6116953086b --- /dev/null +++ b/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm4_defconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2025 PHYTEC America LLC +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm7.dts b/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm7.dts new file mode 100644 index 000000000000..4126187008d0 --- /dev/null +++ b/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm7.dts @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2025 PHYTEC America LLC + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "phyboard_atlas.dtsi" + +/ { + model = "PHYTEC phyBOARD-Atlas i.MX RT1170 CM7"; + compatible = "phytec,phyboard_atlas"; + + aliases { + mipi-dsi = &mipi_dsi; + }; + + chosen { + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + zephyr,canbus = &flexcan3; + }; + + nxp_mipi_connector: mipi-connector { + compatible = "gpio-nexus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio9 29 0>, /* Pin 1, LEDK */ + <21 0 &gpio9 30 0>, /* Pin 21, RESET */ + <26 0 &gpio6 8 0>, /* Pin 26, CTP_I2C SDA */ + <27 0 &gpio6 9 0>, /* Pin 27, CTP_I2C SCL */ + <28 0 &gpio9 0 0>, /* Pin 28, CTP_RST */ + <29 0 &gpio8 31 0>, /* Pin 29, CTP_INT */ + <32 0 &gpio11 16 0>, /* Pin 32, PWR_EN */ + <34 0 &gpio9 29 0>; /* Pin 34, BL_PWM */ + }; +}; + +&user_button { + status = "okay"; +}; + +&board_green_led { + status = "okay"; +}; + +&board_red_led { + status = "okay"; +}; + +&flexcan3 { + status = "okay"; + phys = <&transceiver0>; +}; + +&lpspi1 { + dmas = <&edma0 0 36>, <&edma0 1 37>; + dma-names = "rx", "tx"; + status = "okay"; +}; + +&edma0 { + status = "okay"; +}; + +&lpuart1 { + status = "okay"; + current-speed = <115200>; +}; + +&lpuart5 { + status = "okay"; + current-speed = <115200>; +}; + +&lpuart8 { + status = "okay"; + current-speed = <115200>; +}; + +nxp_mipi_i2c: &lpi2c5 { + pinctrl-0 = <&pinmux_lpi2c5>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; +}; + +&sai1 { + status = "okay"; +}; + +zephyr_udc0: &usb1 { + status = "okay"; + phy-handle = <&usbphy1>; +}; + +&usbphy1 { + status = "okay"; + tx-d-cal = <7>; + tx-cal-45-dp-ohms = <6>; + tx-cal-45-dm-ohms = <6>; +}; + +zephyr_udc1: &usb2 { + status = "okay"; + phy-handle = <&usbphy2>; +}; + +&usbphy2 { + status = "okay"; + tx-d-cal = <7>; + tx-cal-45-dp-ohms = <6>; + tx-cal-45-dm-ohms = <6>; +}; + +&usdhc1 { + status = "okay"; + detect-dat3; + no-1-8-v; + + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; +}; + +zephyr_lcdif: &lcdif {}; + +zephyr_mipi_dsi: &mipi_dsi { + dphy-ref-frequency = <24000000>; +}; diff --git a/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm7.yaml b/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm7.yaml new file mode 100644 index 000000000000..e42d9304dcdc --- /dev/null +++ b/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm7.yaml @@ -0,0 +1,29 @@ +# Copyright (c) 2025 PHYTEC America LLC +# SPDX-License-Identifier: Apache-2.0 + +identifier: phyboard_atlas/mimxrt1176/cm7 +name: PHYTEC phyBOARD-Atlas i.MX RT1170 CM7 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 256 +flash: 16384 +supported: + - can + - dac + - display + - dma + - flash + - gpio + - i2c + - i2s + - mipi_dsi + - netif:eth + - spi + - uart + - usb_device + - usbd +vendor: phytec diff --git a/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm7_defconfig b/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm7_defconfig new file mode 100644 index 000000000000..b6116953086b --- /dev/null +++ b/boards/phytec/phyboard_atlas/phyboard_atlas_mimxrt1176_cm7_defconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2025 PHYTEC America LLC +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/dts/arm/phytec/phycore_rt1170-pinctrl.dtsi b/dts/arm/phytec/phycore_rt1170-pinctrl.dtsi new file mode 100644 index 000000000000..139e06d1ce21 --- /dev/null +++ b/dts/arm/phytec/phycore_rt1170-pinctrl.dtsi @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2025 PHYTEC America LLC + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + pinmux_enet1g: pinmux_enet1g { + group0 { + pinmux = <&iomuxc_gpio_disp_b1_11_enet_1g_tx_clk_io>, // ENET_RGMII_TXC + <&iomuxc_gpio_disp_b1_01_enet_1g_rx_clk>; // ENET_RGMII_RXC + bias-disable; + drive-strength = "high"; + slew-rate = "fast"; + input-enable; + }; + + group1 { + pinmux = <&iomuxc_gpio_disp_b1_09_enet_1g_tdata00>, // ENET_RGMII_TXD0 + <&iomuxc_gpio_disp_b1_08_enet_1g_tdata01>, // ENET_RGMII_TXD1 + <&iomuxc_gpio_disp_b1_07_enet_1g_tdata02>, // ENET_RGMII_TXD2 + <&iomuxc_gpio_disp_b1_06_enet_1g_tdata03>, // ENET_RGMII_TXD3 + <&iomuxc_gpio_disp_b1_10_enet_1g_tx_en>; // ENET_RGMII_TX_EN + drive-strength = "high"; + bias-pull-up; + slew-rate = "fast"; + }; + + group2 { + pinmux = <&iomuxc_gpio_disp_b1_02_enet_1g_rdata00>, // ENET_RGMII_RXD0 + <&iomuxc_gpio_disp_b1_03_enet_1g_rdata01>, // ENET_RGMII_RXD1 + <&iomuxc_gpio_disp_b1_04_enet_1g_rdata02>, // ENET_RGMII_RXD2 + <&iomuxc_gpio_disp_b1_05_enet_1g_rdata03>, // ENET_RGMII_RXD3 + <&iomuxc_gpio_disp_b1_00_enet_1g_rx_en>; // ENET_RGMII_RX_EN + drive-strength = "high"; + bias-pull-down; + slew-rate = "fast"; + input-enable; + }; + }; + + pinmux_enet1g_mdio: pinmux_enet1g_mdio { + group0 { + pinmux = <&iomuxc_gpio_emc_b2_19_enet_1g_mdc>, + <&iomuxc_gpio_emc_b2_20_enet_1g_mdio>; + drive-strength = "high"; + bias-pull-down; + slew-rate = "fast"; + }; + + group1 { + pinmux = <&iomuxc_gpio_disp_b2_01_gpio_mux5_io02>; // ETHPHY_RST + drive-strength = "high"; + bias-pull-down; + slew-rate = "slow"; + }; + }; + + pinmux_flexspi1: pinmux_flexspi1 { + group0 { + pinmux = <&iomuxc_gpio_sd_b2_05_flexspi1_a_dqs>, + <&iomuxc_gpio_sd_b2_06_flexspi1_a_ss0_b>, + <&iomuxc_gpio_sd_b2_07_flexspi1_a_sclk>, + <&iomuxc_gpio_sd_b2_08_flexspi1_a_data00>, + <&iomuxc_gpio_sd_b2_09_flexspi1_a_data01>, + <&iomuxc_gpio_sd_b2_10_flexspi1_a_data02>, + <&iomuxc_gpio_sd_b2_11_flexspi1_a_data03>; + bias-pull-down; + input-enable; + }; + }; + + pinmux_lpi2c2: pinmux_lpi2c2 { + group0 { + pinmux = <&iomuxc_gpio_ad_18_lpi2c2_scl>, + <&iomuxc_gpio_ad_19_lpi2c2_sda>; + drive-strength = "normal"; + drive-open-drain; + slew-rate = "fast"; + input-enable; + }; + }; +}; diff --git a/dts/arm/phytec/phycore_rt1170_common.dtsi b/dts/arm/phytec/phycore_rt1170_common.dtsi new file mode 100644 index 000000000000..6396ac1e3fa0 --- /dev/null +++ b/dts/arm/phytec/phycore_rt1170_common.dtsi @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2025 PHYTEC America LLC + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + sdram0: memory@80000000 { + /* MT48LC16M16A2B4-7EIT */ + device_type = "memory"; + reg = <0x80000000 DT_SIZE_M(64)>; + }; + + leds { + compatible = "gpio-leds"; + + som_green_led: led-1 { + gpios = <&gpio13 12 GPIO_ACTIVE_HIGH>; + label = "Green LED D8"; + }; + + som_red_led: led-2 { + gpios = <&gpio13 11 GPIO_ACTIVE_HIGH>; + label = "Red LED D7"; + }; + }; +}; + +&lpi2c2 { + pinctrl-0 =<&pinmux_lpi2c2>; + pinctrl-names = "default"; + status = "okay"; + + eeprom0: eeprom@50 { + compatible = "st,m24xxx", "atmel,at24"; + reg = <0x50>; + status = "okay"; + size = <256>; + pagesize = <8>; + address-width = <16>; + timeout = <5>; + }; +}; + +&enet1g { + status = "okay"; +}; + +&enet1g_mac { + status = "okay"; + pinctrl-0 = <&pinmux_enet1g>; + pinctrl-names = "default"; + phy-handle = <&enet1g_phy>; + phy-connection-type = "rgmii"; + zephyr,random-mac-address; +}; + +&enet1g_mdio { + status = "okay"; + pinctrl-0 = <&pinmux_enet1g_mdio>; + pinctrl-names = "default"; + + enet1g_phy: phy@0 { + compatible = "ti,dp83867"; + reg = <0>; + status = "okay"; + reset-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; + int-gpios = <&gpio5 15 GPIO_ACTIVE_LOW>; + }; +}; + +&flexspi { + pinctrl-0 = <&pinmux_flexspi1>; + pinctrl-names = "default"; +}; + +&flexspi { + status = "okay"; + ahb-prefetch; + ahb-read-addr-opt; + rx-clock-source = <1>; + reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(16)>; + + mx25u12832f: mx25u12832f@0 { + compatible = "nxp,imx-flexspi-nor"; + /* MX25U12832FM2I02 is 16MB, 128MBit flash part */ + size = ; + reg = <0>; + spi-max-frequency = <100000000>; + status = "okay"; + jedec-id = [c2 25 38]; + erase-block-size = <4096>; + write-block-size = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(128)>; + }; + /* Note slot 0 has one additional sector, + * this is intended for use with the swap move algorithm + */ + slot0_partition: partition@20000 { + label = "image-0"; + reg = <0x00020000 0x301000>; + }; + slot1_partition: partition@321000 { + label = "image-1"; + reg = <0x00321000 0x300000>; + }; + storage_partition: partition@621000 { + label = "storage"; + reg = <0x00621000 DT_SIZE_K(1984)>; + }; + }; + }; +}; diff --git a/dts/arm/phytec/phycore_rt1170_mimxrt1176_cm4.dtsi b/dts/arm/phytec/phycore_rt1170_mimxrt1176_cm4.dtsi new file mode 100644 index 000000000000..83e2d7f5eeed --- /dev/null +++ b/dts/arm/phytec/phycore_rt1170_mimxrt1176_cm4.dtsi @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2025 PHYTEC America LLC + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +/ { + chosen { + /* + * Note: when using DMA, the SRAM region must be set to + * a memory region that is not cached by the chip. If the chosen + * sram region is changed and DMA is in use, you will + * encounter issues! + */ + zephyr,sram = &sram1; + zephyr,flash-controller = &mx25u12832f; + zephyr,flash = &ocram; + nxp,m4-partition = &slot1_partition; + zephyr,ipc = &mailbox_b; + }; + + zephyr,user { + dac = <&dac>; + dac-channel-id = <0>; + dac-resolution = <12>; + }; +}; + +&dac { + status = "okay"; +}; + +&lpuart6 { + status = "okay"; + current-speed = <115200>; +}; + +&som_green_led { + status = "okay"; +}; + +&som_red_led { + status = "okay"; +}; + +/* GPT and Systick are enabled. If power management is enabled, the GPT + * timer will be used instead of systick, as allows the core clock to + * be gated. + */ +&gpt_hw_timer { + status = "okay"; +}; + +&systick { + status = "okay"; +}; + +&edma_lpsr0 { + status = "okay"; +}; + +&mailbox_b { + status = "okay"; +}; diff --git a/dts/arm/phytec/phycore_rt1170_mimxrt1176_cm7.dtsi b/dts/arm/phytec/phycore_rt1170_mimxrt1176_cm7.dtsi new file mode 100644 index 000000000000..d23a8d058b90 --- /dev/null +++ b/dts/arm/phytec/phycore_rt1170_mimxrt1176_cm7.dtsi @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2025 PHYTEC America LLC + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +/ { + chosen { + zephyr,sram = &sdram0; + zephyr,dtcm = &dtcm; + zephyr,itcm = &itcm; + zephyr,flash-controller = &mx25u12832f; + zephyr,flash = &mx25u12832f; + zephyr,code-partition = &slot0_partition; + zephyr,cpu1-region = &ocram; + zephyr,ipc = &mailbox_a; + }; + + zephyr,user { + dac = <&dac>; + dac-channel-id = <0>; + dac-resolution = <12>; + }; +}; + +&dac { + status = "okay"; +}; + +&lpuart1 { + status = "okay"; + current-speed = <115200>; +}; + +&lpuart5 { + status = "okay"; + current-speed = <115200>; +}; + +&som_green_led { + status = "okay"; +}; + +&som_red_led { + status = "okay"; +}; + +/* GPT and Systick are enabled. If power management is enabled, the GPT + * timer will be used instead of systick, as allows the core clock to + * be gated. + */ +&gpt_hw_timer { + status = "okay"; +}; + +&systick { + status = "okay"; +}; + +&wdog1 { + status = "okay"; +}; + +&mailbox_a { + status = "okay"; +}; + +&pit1 { + status = "okay"; +}; + +&pit2 { + status = "okay"; +};