-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathgtnlv.log
277 lines (277 loc) · 17.1 KB
/
gtnlv.log
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
# Copyright (C) 1994-2016, Concept Engineering GmbH.
# All Rights Reserved. Cmd=logfile.
# Nlview 6.6.8 2016-12-21 bk=1.3817 VDI=40 GEI=35 GUI=JA:1.6
# License cookie [G|T|S|*] for HR="Xilinx Inc."
# -----------------------------------------------------------------------------
# -----------------------------------------------------------------------------
property showattribute 1
property showcellname true
property shadowstyle 1
property gatecellname 2
property showpinname 2
property showhierpinname 2
property showinstname false
property boxpinsquare 2
property boxhierpins 2
property backgroundcolor #F8F8FF
property boxinstcolor #000000
property boxcolor0 #000000
property boxpincolor #000000
property netcolor #000000
property buscolor #000000
property portcolor #000000
property portnamecolor #000000
property boxminwidth 50
property boxminheight 40
module new gtmodule
# * Current module is gtmodule
load symbol QUAD v HIERBOX port i0 in port i1 in port i2 in port i3 in port i4 in
load symbol {CHANNEL PLL} syn BOX port In in port Out out text CPLL -cc 25 0 12
load symbol {QUAD PLL} syn BOX port In in port Out out text QPLL -cc 25 0 12
load port REFCLK1_Q3 in -pg 1 -y 121 -x 1 -attr @fillcolor #3a5fcd
load port REFCLK0_Q3 in -pg 1 -y 191 -x 1 -attr @fillcolor #3a5fcd
load inst Quad3 QUAD v -pg 1 -y 1 -x 2000 -autohide -attr @cell Quad3 -attr @name {} -attr @fillcolor #d9d9d9
attribute {pin Quad3 i0 } -attr @name {}
attribute {pin Quad3 i1 } -attr @name {}
attribute {pin Quad3 i2 } -attr @name {}
attribute {pin Quad3 i3 } -attr @name {}
attribute {pin Quad3 i4 } -attr @name {}
attribute {hierPin Quad3 i0 } -attr @name {}
attribute {hierPin Quad3 i1 } -attr @name {}
attribute {hierPin Quad3 i2 } -attr @name {}
attribute {hierPin Quad3 i3 } -attr @name {}
attribute {hierPin Quad3 i4 } -attr @name {}
load inst cpll.3.3 {CHANNEL PLL} syn -hier Quad3 -pg 1 -y 2 -x 1 -autohide -attr @name {} -attr @cell {} -attr @fillcolor #00868b
attribute {pin cpll.3.3 In} -attr @name {}
attribute {pin cpll.3.3 Out} -attr @name {}
load symbol GTX_X0Y15 syn HIERGEN port TX in port RX in
load inst GT.3.3 GTX_X0Y15 syn -hier Quad3 -pg 1 -y 2 -x 2 -attr @name {} -attr @fillcolor #7a7a7a
load inst cpll.3.2 {CHANNEL PLL} syn -hier Quad3 -pg 1 -y 87 -x 1 -autohide -attr @name {} -attr @cell {} -attr @fillcolor #00868b
attribute {pin cpll.3.2 In} -attr @name {}
attribute {pin cpll.3.2 Out} -attr @name {}
load symbol GTX_X0Y14 syn HIERGEN port TX in port RX in
load inst GT.3.2 GTX_X0Y14 syn -hier Quad3 -pg 1 -y 87 -x 2 -attr @name {} -attr @fillcolor #7a7a7a
load inst qpll.3 {QUAD PLL} syn -hier Quad3 -pg 1 -y 172 -x 1 -autohide -attr @name {} -attr @cell {} -attr @fillcolor #00868b
attribute {pin qpll.3 In} -attr @name {}
attribute {pin qpll.3 Out} -attr @name {}
load inst cpll.3.1 {CHANNEL PLL} syn -hier Quad3 -pg 1 -y 257 -x 1 -autohide -attr @name {} -attr @cell {} -attr @fillcolor #00868b
attribute {pin cpll.3.1 In} -attr @name {}
attribute {pin cpll.3.1 Out} -attr @name {}
load symbol GTX_X0Y13 syn HIERGEN port TX in port RX in
load inst GT.3.1 GTX_X0Y13 syn -hier Quad3 -pg 1 -y 257 -x 2 -attr @name {} -attr @fillcolor #7a7a7a
load inst cpll.3.0 {CHANNEL PLL} syn -hier Quad3 -pg 1 -y 342 -x 1 -autohide -attr @name {} -attr @cell {} -attr @fillcolor #00868b
attribute {pin cpll.3.0 In} -attr @name {}
attribute {pin cpll.3.0 Out} -attr @name {}
load symbol GTX_X0Y12 syn HIERGEN port TX in port RX in
load inst GT.3.0 GTX_X0Y12 syn -hier Quad3 -pg 1 -y 342 -x 2 -attr @name {} -attr @fillcolor #7a7a7a
load port REFCLK1_Q2 in -pg 1 -y 581 -x 1 -attr @fillcolor #3a5fcd
load port REFCLK0_Q2 in -pg 1 -y 651 -x 1 -attr @fillcolor #3a5fcd
load inst Quad2 QUAD v -pg 1 -y 461 -x 2000 -autohide -attr @cell Quad2 -attr @name {} -attr @fillcolor #d9d9d9
attribute {pin Quad2 i0 } -attr @name {}
attribute {pin Quad2 i1 } -attr @name {}
attribute {pin Quad2 i2 } -attr @name {}
attribute {pin Quad2 i3 } -attr @name {}
attribute {pin Quad2 i4 } -attr @name {}
attribute {hierPin Quad2 i0 } -attr @name {}
attribute {hierPin Quad2 i1 } -attr @name {}
attribute {hierPin Quad2 i2 } -attr @name {}
attribute {hierPin Quad2 i3 } -attr @name {}
attribute {hierPin Quad2 i4 } -attr @name {}
load inst cpll.2.3 {CHANNEL PLL} syn -hier Quad2 -pg 1 -y 462 -x 1 -autohide -attr @name {} -attr @cell {} -attr @fillcolor #00868b
attribute {pin cpll.2.3 In} -attr @name {}
attribute {pin cpll.2.3 Out} -attr @name {}
load symbol GTX_X0Y11 syn HIERGEN port TX in port RX in
load inst GT.2.3 GTX_X0Y11 syn -hier Quad2 -pg 1 -y 462 -x 2 -attr @name {} -attr @fillcolor #7a7a7a
load inst cpll.2.2 {CHANNEL PLL} syn -hier Quad2 -pg 1 -y 547 -x 1 -autohide -attr @name {} -attr @cell {} -attr @fillcolor #00868b
attribute {pin cpll.2.2 In} -attr @name {}
attribute {pin cpll.2.2 Out} -attr @name {}
load symbol GTX_X0Y10 syn HIERGEN port TX in port RX in
load inst GT.2.2 GTX_X0Y10 syn -hier Quad2 -pg 1 -y 547 -x 2 -attr @name {} -attr @fillcolor #7a7a7a
load inst qpll.2 {QUAD PLL} syn -hier Quad2 -pg 1 -y 632 -x 1 -autohide -attr @name {} -attr @cell {} -attr @fillcolor #00868b
attribute {pin qpll.2 In} -attr @name {}
attribute {pin qpll.2 Out} -attr @name {}
load inst cpll.2.1 {CHANNEL PLL} syn -hier Quad2 -pg 1 -y 717 -x 1 -autohide -attr @name {} -attr @cell {} -attr @fillcolor #00868b
attribute {pin cpll.2.1 In} -attr @name {}
attribute {pin cpll.2.1 Out} -attr @name {}
load symbol GTX_X0Y9 syn HIERGEN port TX in port RX in
load inst GT.2.1 GTX_X0Y9 syn -hier Quad2 -pg 1 -y 717 -x 2 -attr @name {} -attr @fillcolor #7a7a7a
load inst cpll.2.0 {CHANNEL PLL} syn -hier Quad2 -pg 1 -y 802 -x 1 -autohide -attr @name {} -attr @cell {} -attr @fillcolor #00868b
attribute {pin cpll.2.0 In} -attr @name {}
attribute {pin cpll.2.0 Out} -attr @name {}
load symbol GTX_X0Y8 syn HIERGEN port TX in port RX in
load inst GT.2.0 GTX_X0Y8 syn -hier Quad2 -pg 1 -y 802 -x 2 -attr @name {} -attr @fillcolor #7a7a7a
load port REFCLK1_Q1 in -pg 1 -y 1041 -x 1 -attr @fillcolor #3a5fcd
load port REFCLK0_Q1 in -pg 1 -y 1111 -x 1 -attr @fillcolor #3a5fcd
load inst Quad1 QUAD v -pg 1 -y 921 -x 2000 -autohide -attr @cell Quad1 -attr @name {} -attr @fillcolor #d9d9d9
attribute {pin Quad1 i0 } -attr @name {}
attribute {pin Quad1 i1 } -attr @name {}
attribute {pin Quad1 i2 } -attr @name {}
attribute {pin Quad1 i3 } -attr @name {}
attribute {pin Quad1 i4 } -attr @name {}
attribute {hierPin Quad1 i0 } -attr @name {}
attribute {hierPin Quad1 i1 } -attr @name {}
attribute {hierPin Quad1 i2 } -attr @name {}
attribute {hierPin Quad1 i3 } -attr @name {}
attribute {hierPin Quad1 i4 } -attr @name {}
load inst cpll.1.3 {CHANNEL PLL} syn -hier Quad1 -pg 1 -y 922 -x 1 -autohide -attr @name {} -attr @cell {} -attr @fillcolor #00868b
attribute {pin cpll.1.3 In} -attr @name {}
attribute {pin cpll.1.3 Out} -attr @name {}
load symbol GTX_X0Y7 syn HIERGEN port TX in port RX in
load inst GT.1.3 GTX_X0Y7 syn -hier Quad1 -pg 1 -y 922 -x 2 -attr @name {} -attr @fillcolor #7a7a7a
load inst cpll.1.2 {CHANNEL PLL} syn -hier Quad1 -pg 1 -y 1007 -x 1 -autohide -attr @name {} -attr @cell {} -attr @fillcolor #00868b
attribute {pin cpll.1.2 In} -attr @name {}
attribute {pin cpll.1.2 Out} -attr @name {}
load symbol GTX_X0Y6 syn HIERGEN port TX in port RX in
load inst GT.1.2 GTX_X0Y6 syn -hier Quad1 -pg 1 -y 1007 -x 2 -attr @name {} -attr @fillcolor #7a7a7a
load inst qpll.1 {QUAD PLL} syn -hier Quad1 -pg 1 -y 1092 -x 1 -autohide -attr @name {} -attr @cell {} -attr @fillcolor #00868b
attribute {pin qpll.1 In} -attr @name {}
attribute {pin qpll.1 Out} -attr @name {}
load inst cpll.1.1 {CHANNEL PLL} syn -hier Quad1 -pg 1 -y 1177 -x 1 -autohide -attr @name {} -attr @cell {} -attr @fillcolor #00868b
attribute {pin cpll.1.1 In} -attr @name {}
attribute {pin cpll.1.1 Out} -attr @name {}
load symbol GTX_X0Y5 syn HIERGEN port TX in port RX in
load inst GT.1.1 GTX_X0Y5 syn -hier Quad1 -pg 1 -y 1177 -x 2 -attr @name {} -attr @fillcolor #7a7a7a
load inst cpll.1.0 {CHANNEL PLL} syn -hier Quad1 -pg 1 -y 1262 -x 1 -autohide -attr @name {} -attr @cell {} -attr @fillcolor #00868b
attribute {pin cpll.1.0 In} -attr @name {}
attribute {pin cpll.1.0 Out} -attr @name {}
load symbol GTX_X0Y4 syn HIERGEN port TX in port RX in
load inst GT.1.0 GTX_X0Y4 syn -hier Quad1 -pg 1 -y 1262 -x 2 -attr @name {} -attr @fillcolor #7a7a7a
load port REFCLK1_Q0 in -pg 1 -y 1501 -x 1 -attr @fillcolor #3a5fcd
load port REFCLK0_Q0 in -pg 1 -y 1571 -x 1 -attr @fillcolor #3a5fcd
load inst Quad0 QUAD v -pg 1 -y 1381 -x 2000 -autohide -attr @cell Quad0 -attr @name {} -attr @fillcolor #d9d9d9
attribute {pin Quad0 i0 } -attr @name {}
attribute {pin Quad0 i1 } -attr @name {}
attribute {pin Quad0 i2 } -attr @name {}
attribute {pin Quad0 i3 } -attr @name {}
attribute {pin Quad0 i4 } -attr @name {}
attribute {hierPin Quad0 i0 } -attr @name {}
attribute {hierPin Quad0 i1 } -attr @name {}
attribute {hierPin Quad0 i2 } -attr @name {}
attribute {hierPin Quad0 i3 } -attr @name {}
attribute {hierPin Quad0 i4 } -attr @name {}
load inst cpll.0.3 {CHANNEL PLL} syn -hier Quad0 -pg 1 -y 1382 -x 1 -autohide -attr @name {} -attr @cell {} -attr @fillcolor #00868b
attribute {pin cpll.0.3 In} -attr @name {}
attribute {pin cpll.0.3 Out} -attr @name {}
load symbol GTX_X0Y3 syn HIERGEN port TX in port RX in
load inst GT.0.3 GTX_X0Y3 syn -hier Quad0 -pg 1 -y 1382 -x 2 -attr @name {} -attr @fillcolor #7a7a7a
load inst cpll.0.2 {CHANNEL PLL} syn -hier Quad0 -pg 1 -y 1467 -x 1 -autohide -attr @name {} -attr @cell {} -attr @fillcolor #00868b
attribute {pin cpll.0.2 In} -attr @name {}
attribute {pin cpll.0.2 Out} -attr @name {}
load symbol GTX_X0Y2 syn HIERGEN port TX in port RX in
load inst GT.0.2 GTX_X0Y2 syn -hier Quad0 -pg 1 -y 1467 -x 2 -attr @name {} -attr @fillcolor #7a7a7a
load inst qpll.0 {QUAD PLL} syn -hier Quad0 -pg 1 -y 1552 -x 1 -autohide -attr @name {} -attr @cell {} -attr @fillcolor #00868b
attribute {pin qpll.0 In} -attr @name {}
attribute {pin qpll.0 Out} -attr @name {}
load inst cpll.0.1 {CHANNEL PLL} syn -hier Quad0 -pg 1 -y 1637 -x 1 -autohide -attr @name {} -attr @cell {} -attr @fillcolor #00868b
attribute {pin cpll.0.1 In} -attr @name {}
attribute {pin cpll.0.1 Out} -attr @name {}
load symbol GTX_X0Y1 syn HIERGEN port TX in port RX in
load inst GT.0.1 GTX_X0Y1 syn -hier Quad0 -pg 1 -y 1637 -x 2 -attr @name {} -attr @fillcolor #7a7a7a
load inst cpll.0.0 {CHANNEL PLL} syn -hier Quad0 -pg 1 -y 1722 -x 1 -autohide -attr @name {} -attr @cell {} -attr @fillcolor #00868b
attribute {pin cpll.0.0 In} -attr @name {}
attribute {pin cpll.0.0 Out} -attr @name {}
load symbol GTX_X0Y0 syn HIERGEN port TX in port RX in
load inst GT.0.0 GTX_X0Y0 syn -hier Quad0 -pg 1 -y 1722 -x 2 -attr @name {} -attr @fillcolor #7a7a7a
load net net.REFCLK1_Q0 -port REFCLK1_Q0 -pin Quad0 i4
load net net.Quad0.qpll -hierPin Quad0 i4 -pin qpll.0 In
load net net.quadpll.0 -pin qpll.0 Out -pin GT.0.1 TX
attribute {inst qpll.0} -attr @fillcolor #cccc00
attribute {inst GT.0.1} -attr @fillcolor #cccc00
load net net.REFCLK1_Q0 -port REFCLK1_Q0 -pin Quad0 i4
load net net.Quad0.qpll -hierPin Quad0 i4 -pin qpll.0 In
load net net.quadpll.0 -pin qpll.0 Out -pin GT.0.1 RX
attribute {inst qpll.0} -attr @fillcolor #cccc00
attribute {inst GT.0.1} -attr @fillcolor #cccc00
load net net.REFCLK1_Q0 -port REFCLK1_Q0 -pin Quad0 i4
load net net.Quad0.qpll -hierPin Quad0 i4 -pin qpll.0 In
load net net.quadpll.0 -pin qpll.0 Out -pin GT.0.2 TX
attribute {inst qpll.0} -attr @fillcolor #cccc00
attribute {inst GT.0.2} -attr @fillcolor #cccc00
load net net.REFCLK1_Q0 -port REFCLK1_Q0 -pin Quad0 i4
load net net.Quad0.qpll -hierPin Quad0 i4 -pin qpll.0 In
load net net.quadpll.0 -pin qpll.0 Out -pin GT.0.2 RX
attribute {inst qpll.0} -attr @fillcolor #cccc00
attribute {inst GT.0.2} -attr @fillcolor #cccc00
show
# Starting Split Pages 77.95
# Split Pages 48 Comps, 3 Nets 0 NetBundles 78.01
# KwayPart started for 48 comps, 3 nets 78.01
# Init done: 1 nodes (1 locked nodes), 0 edges 78.01
# Startpart done: 1 parts 78.03
# KwayPart done 78.03
# End of Split Pages: 1 pages 78.05
# End of Split Pages 78.05
# Generating Regions for Page 1: 48 Comps, 3 Nets 78.05
# Analyze 78.05
# Levelize 78.05
# End of LevelAssign mode=I, 3 Levels, 9 Comps, limit=30000 78.05
# Nets 78.05
# Place 78.05
# PlaceNets 78.05
# SpaceY 78.05
# Track 78.06
# SpaceX 78.06
# Wire 78.06
# End of Wire: 0 nets, 0 ch, wire: 0-->0 (0 with wbits) 78.06
# End of doGenerate 78.06
# Analyze 78.06
# Levelize 78.06
# End of LevelAssign mode=I, 3 Levels, 9 Comps, limit=30000 78.06
# Nets 78.06
# Place 78.06
# PlaceNets 78.06
# SpaceY 78.06
# Track 78.06
# SpaceX 78.06
# Wire 78.06
# End of Wire: 0 nets, 0 ch, wire: 0-->0 (0 with wbits) 78.06
# End of doGenerate 78.06
# Analyze 78.06
# Levelize 78.06
# End of LevelAssign mode=I, 3 Levels, 9 Comps, limit=30000 78.06
# Nets 78.06
# Place 78.06
# PlaceNets 78.06
# SpaceY 78.06
# Track 78.06
# SpaceX 78.06
# Wire 78.06
# End of Wire: 0 nets, 0 ch, wire: 0-->0 (0 with wbits) 78.06
# End of doGenerate 78.06
# Analyze 78.06
# Levelize 78.06
# End of LevelAssign mode=I, 3 Levels, 10 Comps, limit=30000 78.06
# Nets 78.06
# Place 78.06
# PlaceNets 78.06
# SpaceY 78.06
# Track 78.06
# SpaceX 78.06
# Wire 78.06
# End of Wire: 2 nets, 2 ch, wire: 18-->18 (0 with wbits) 78.06
# End of doGenerate 78.06
# Analyze 78.06
# Levelize 78.06
# End of LevelAssign mode=I, 2 Levels, 12 Comps, limit=30000 78.06
# Nets 78.06
# Place 78.06
# PlaceNets 78.06
# SpaceY 78.06
# Track 78.06
# SpaceX 78.06
# Wire 78.06
# End of Wire: 1 nets, 1 ch, wire: 4-->4 (0 with wbits) 78.06
# End of doGenerate 78.06
# End of Generating Regions for Page 1 78.06
scrollpos 88 772
zoom -x 0 -y 0 0.68
scrollpos 75 656
#R 0.68
center_objects -itemized {inst GT.0.2}
scrollpos 176 1058
#CMD scrollpos
#R 176 1058
#CMD scrollpos -10 1058
scrollpos -10 1058
selection -itemized {inst GT.0.0}
scrollpos -10 1058