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LukiLeu · Nov 24, 2020 · b553d8d · b553d8d
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diff --git a/VHDL/adc/adc.vhd b/VHDL/adc/adc.vhd
@@ -1,10 +1,13 @@
 ----------------------------------------------------------------------------------------------------
--- brief: This VHDL file implements the full ADC.
--- file: tdc.vhd
+-- brief: This file implements a slope ADC which uses the output impedance in the ouput buffers to 
+--        create a reference slope which is then compared to the signal-to-be-measured. A TDC 
+--        measures the time from the beginning of the slope until the slope crosses the voltage-to-
+--        be-measured. Different linearization and correction techniques are also deployed.
+-- file: adc.vhd
 -- author: Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 -- File history:
 --

diff --git a/VHDL/calcMean/calcMean.vhd b/VHDL/calcMean/calcMean.vhd
@@ -1,10 +1,10 @@
 ----------------------------------------------------------------------------------------------------
--- project		Calculates the mean over n samples			
--- file			calcMean.vhd
--- author		Lukas Leuenberger
+-- brief: This block calcualtes the mean values over n samples.
+-- file: calcMean.vhd
+-- author: Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 --  File history:
 --

diff --git a/VHDL/calcMean/calcMean_tb.vhd b/VHDL/calcMean/calcMean_tb.vhd
@@ -3,8 +3,8 @@
 -- file: calcMean_tb.vhd
 -- author: Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 -- File history:
 --

diff --git a/VHDL/calibrationTDCAlign/calibrationTDCAlign.vhd b/VHDL/calibrationTDCAlign/calibrationTDCAlign.vhd
@@ -1,10 +1,10 @@
 ----------------------------------------------------------------------------------------------------
--- brief: calibrationTDCAlign - Führt den Kalibrationsvorgang für den TDC aus
+-- brief: This block calibrates the aligning of the delay chain with the slope.
 -- file: calibrationTDCAlign.vhd
 -- author: Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 -- File history:
 --

diff --git a/VHDL/calibrationTDCAlign/calibrationTDCAlign_tb.vhd b/VHDL/calibrationTDCAlign/calibrationTDCAlign_tb.vhd
@@ -3,8 +3,8 @@
 -- file: calibrationTDCAlign_tb.vhd
 -- author: Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 -- File history:
 --

diff --git a/VHDL/calibrationTDCLength/calibrationTDCLength.vhd b/VHDL/calibrationTDCLength/calibrationTDCLength.vhd
@@ -1,10 +1,11 @@
 ----------------------------------------------------------------------------------------------------
--- brief: calibrationTDCLength - Führt den Kalibrationsvorgang für den TDC aus
+-- brief: This block calibrates the length of the delay chain, eg. the number of taps which
+--        correspond to one clock period are determined.
 -- file: calibrationTDCLength.vhd
 -- author: Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 -- File history:
 --

diff --git a/VHDL/calibrationTDCLength/calibrationTDCLength_tb.vhd b/VHDL/calibrationTDCLength/calibrationTDCLength_tb.vhd
@@ -3,8 +3,8 @@
 -- file: calibrationTDCLength_tb.vhd
 -- author: Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 -- File history:
 --

diff --git a/VHDL/carryChain/carryChain.vhd b/VHDL/carryChain/carryChain.vhd
@@ -1,10 +1,10 @@
 ----------------------------------------------------------------------------------------------------
--- brief: carryChain - Carry Chain
+-- brief: This block implements a carry chain.
 -- file: carryChain.vhd
 -- author: Felix Haller, Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 -- This VHDL code is initially based on code written by h.a.r.homulle@tudelft.nl found on http://cas.tudelft.nl/fpga_tdc/TDC_basic.html	
 ----------------------------------------------------------------------------------------------------
 -- File history:

diff --git a/VHDL/carryDelay/carryDelay.vhd b/VHDL/carryDelay/carryDelay.vhd
@@ -1,10 +1,10 @@
 ----------------------------------------------------------------------------------------------------
--- brief: carryDelay - Applies a configurable delay before the signal enters the carry chain
+-- brief: This block applies a configurable delay before the signal enters the carry chain.
 -- file: carryDelay.vhd
 -- author: Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 -- File history:
 --

diff --git a/VHDL/diffInputPad/diffInputPad.vhd b/VHDL/diffInputPad/diffInputPad.vhd
@@ -1,10 +1,11 @@
 ----------------------------------------------------------------------------------------------------
--- brief: diffInputPad
+-- brief: This block instantiates the differential input/output buffer which is used to generate the
+--        reference slope and which contains also the comparator.
 -- file: diffInputPad.vhd
 -- author: Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 -- File history:
 --

diff --git a/VHDL/division/division.vhd b/VHDL/division/division.vhd
@@ -1,10 +1,10 @@
 ----------------------------------------------------------------------------------------------------
--- project: Division		
+-- project: This block performs a division from two values.		
 -- file: division.vhd
 -- author: Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 -- File history:
 --

diff --git a/VHDL/division/divison_tb.vhd b/VHDL/division/divison_tb.vhd
@@ -1,11 +1,10 @@
 ----------------------------------------------------------------------------------------------------
---  project: Division - Testbench
 --  brief: Testbench for the Division block
 --  file: divison_tb.vhd
---  author: Marco Ehrler
+--  author: Marco Ehrler, Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
---  All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 --  File history:
 --

diff --git a/VHDL/dnl/dnl.vhd b/VHDL/dnl/dnl.vhd
@@ -1,10 +1,10 @@
 ----------------------------------------------------------------------------------------------------
--- brief: DNL - Berechnet die DNL aus einem Histogram
+-- brief: Calculates the DNL from a histogram.
 -- file: dnl.vhd
 -- author: Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 -- File history:
 --

diff --git a/VHDL/dnl/dnl_tb.vhd b/VHDL/dnl/dnl_tb.vhd
@@ -3,8 +3,8 @@
 -- file: dnl_tb.vhd
 -- author: Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 -- File history:
 --

diff --git a/VHDL/histogram/histogram.vhd b/VHDL/histogram/histogram.vhd
@@ -1,10 +1,10 @@
 ----------------------------------------------------------------------------------------------------
--- brief: Histogram - Calculates a histogram
+-- brief: This block calculates a histogram.
 -- file: hitsogram.vhd
 -- author: Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 -- File history:
 --

diff --git a/VHDL/histogram/histogram_tb.vhd b/VHDL/histogram/histogram_tb.vhd
@@ -3,8 +3,8 @@
 -- file: histogram_tb.vhd
 -- author: Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 -- File history:
 --

diff --git a/VHDL/inl/inl.vhd b/VHDL/inl/inl.vhd
@@ -1,10 +1,10 @@
 ----------------------------------------------------------------------------------------------------
--- brief: INL - Calculates the INL from a DNL
+-- brief: Calculates the INL from a DNL.
 -- file: inl.vhd
 -- author: Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 -- File history:
 --

diff --git a/VHDL/inl/inl_tb.vhd b/VHDL/inl/inl_tb.vhd
@@ -3,8 +3,8 @@
 -- file: inl_tb.vhd
 -- author: Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 -- File history:
 --

diff --git a/VHDL/inlCorrection/inlCorrection.vhd b/VHDL/inlCorrection/inlCorrection.vhd
@@ -3,8 +3,8 @@
 -- file: inlCorrection.vhd
 -- author: Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 -- File history:
 --

diff --git a/VHDL/inlCorrection/inlCorrectionCalc.vhd b/VHDL/inlCorrection/inlCorrectionCalc.vhd
@@ -3,8 +3,8 @@
 -- file: inlCorrectionCalc.vhd
 -- author: Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 -- File history:
 --

diff --git a/VHDL/inlCorrection/inlCorrectionCalc_tb.vhd b/VHDL/inlCorrection/inlCorrectionCalc_tb.vhd
@@ -3,8 +3,8 @@
 -- file: inlCorrectionCalc_tb.vhd
 -- author: Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 -- File history:
 --

diff --git a/VHDL/inlCorrection/inlCorrectionControl.vhd b/VHDL/inlCorrection/inlCorrectionControl.vhd
@@ -3,8 +3,8 @@
 -- file: inlCorrectionControl.vhd
 -- author: Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 -- File history:
 --

diff --git a/VHDL/inlCorrection/inlCorrectionControl_tb.vhd b/VHDL/inlCorrection/inlCorrectionControl_tb.vhd
@@ -3,8 +3,8 @@
 -- file: inlCorrectionControl_tb.vhd
 -- author: Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 -- File history:
 --

diff --git a/VHDL/lutTransition/lutTransition.vhd b/VHDL/lutTransition/lutTransition.vhd
@@ -1,10 +1,11 @@
 ----------------------------------------------------------------------------------------------------
--- brief: lutTransition - Looks up the corrected value for an input signal and calculates the output value based on this
+-- brief: Looks up the corrected value for an input signal and calculates the output value based on 
+--        this value.
 -- file: lutTransition.vhd
 -- author: Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 -- File history:
 --

diff --git a/VHDL/lutTransition/lutTransition_tb.vhd b/VHDL/lutTransition/lutTransition_tb.vhd
@@ -3,8 +3,8 @@
 -- file: lutTransition_tb.vhd
 -- author: Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 -- File history:
 --

diff --git a/VHDL/pulseDelay/pulseDelay.vhd b/VHDL/pulseDelay/pulseDelay.vhd
@@ -1,10 +1,10 @@
 ----------------------------------------------------------------------------------------------------
--- brief: carryDelay - Applies a configurable delay before the signal enters the carry chain
--- file: carryDelay.vhd
+-- brief: Applies a configurable delay before the clock exits the FPGA through the output buffer
+-- file: pulseDelay.vhd
 -- author: Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 -- File history:
 --

diff --git a/VHDL/tdc/tdc.vhd b/VHDL/tdc/tdc.vhd
@@ -3,8 +3,8 @@
 -- file: tdc.vhd
 -- author: Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 -- File history:
 --

diff --git a/VHDL/tdc/tdcSingle.vhd b/VHDL/tdc/tdcSingle.vhd
@@ -3,8 +3,8 @@
 -- file: tdcSingle.vhd
 -- author: Lukas Leuenberger
 ----------------------------------------------------------------------------------------------------
--- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences
--- All rights reserved.
+-- Copyright (c) 2020 by OST – Eastern Switzerland University of Applied Sciences (www.ost.ch)
+-- This code is licensed under the MIT license (see LICENSE for details)
 ----------------------------------------------------------------------------------------------------
 -- File history:
 --