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20 Open 83 Closed
20 Open 83 Closed
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Issues list

minstret and mcycle
#130 opened Mar 25, 2025 by zhishuohuang9111
External interrupts
#129 opened Mar 13, 2025 by ahemd5
Hit max cycle count (10000000) .. stopping
#128 opened Jan 8, 2025 by noobwei
3
[bug] Case is not fully covered
#127 opened Nov 27, 2024 by likeamahoney
extension `zicsr' required
#125 opened Jun 19, 2024 by ahmdotm
3
tcl file
#124 opened Jun 19, 2024 by ahmdotm
Has the maintenance of this repository been stopped?
#123 opened Jan 9, 2024 by zhangkanqi
1
Not generate waveform when using vcs to test Hello World.
#121 opened Dec 10, 2023 by zhangkanqi
2
coremark/dhrystone testing can't get 4.9 CM/MHz with rtl simulation or in FPGA
#120 opened Oct 26, 2023 by chithize
The new feature of verilator stops building procession
#118 opened Mar 6, 2023 by LoveMyPillow
2
Blocking Loads/DMA disable
#116 opened Jan 24, 2023 by omezrich
Coremark for new extension
#114 opened Dec 15, 2022 by HamzaShabbir517
facing issues when C code size goes beyond 8KB
#111 opened Nov 8, 2022 by yash-agnisys
1
Question about pipeline FF enable signals
#110 opened Jun 13, 2022 by tunefish777
GHR refresh
#107 opened Dec 19, 2021 by Zissi-Lei
1
Usage scenarios of different DFFs
#106 opened Dec 15, 2021 by Zissi-Lei
Unable to replicate performance improvement achieved by using different target values
#105 opened Dec 14, 2021 by samfishman1
1
fpga_optimize cannot be set to 0 in swerv_config
#100 opened Jul 8, 2021 by jlucnagel
1
tlu_flush_path_e4
#90 opened Jan 20, 2021 by kingstone1927
7
Set default mrac value with swerv.config
#84 opened Dec 10, 2020 by olofk
1
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