VHDLinter is a small linter for the VHDL language.
To launch the app, save the repository folder and open the VHDLinter.py script via the console.
VHDLinter offers code check and formating options for VHDL Design Files (.vhd).
Verification of the following VHDL naming and coding conventions is supported:
- VHDL file names are derived by their entity name
- Each line must contain only one VHDL statement
- Source code must not exceed 80 characters per line
- No tab characters should be used for indentation
- Lines must be properly indented with 2 spaces per level of indentation
- Source code should be lower case, except for constant declarations
- Signal and variable names must not exceed 24 characters
- Vector range should be MSB downto LSB
- Constant names should be upper-case
- Ports shoud be ordered by their type (in, out)
- Functionality of entities should be commented
- Functionality of generics should be commented
- Arcitecture names are derived by their entity name and _arc-suffix
- Port maps and generic maps should use named association
- Maps should contain only one port or generic per line
- Package should be indicated by suffixing _pkg to their name
- Self-defined types (except for FSM types) should be in libraries
- Self-defined types should be commented
Automatic correction of the following flaws is possible:
- Removal of bad whitespace
- Removal of trailing whitespaces
- Replacing tabs (Tab2Space)
- Deletion of unused signals or variables
The supported checks and formating options are based on VHDL coding style by Tampere University of Technology and VHDL Style Guide by IMS CHIPS.
This project is licensed under the terms of GNU GPLv3 License.