Allow drawing chip edges in base metal gap

klayout_package/python/kqcircuits/chips/chip.py

@@ -43,7 +43,7 @@
 @add_parameters_from(TsvEllipse, "tsv_elliptical_width")
 @add_parameters_from(FlipChipConnectorRf, "connector_type")
 @add_parameter(ChipFrame, "box", hidden=True)
-@add_parameters_from(ChipFrame, "name_mask", "name_chip", "name_copy", "name_brand",
+@add_parameters_from(ChipFrame, "name_mask", "name_chip", "name_copy", "name_brand", "chip_dicing_in_base_metal",
                      "dice_grid_margin", marker_types=[default_marker_type] * 8)
 class Chip(Element):
     """Base PCell declaration for chips.

klayout_package/python/kqcircuits/elements/chip_frame.py

@@ -53,6 +53,7 @@ class ChipFrame(Element):
     chip_dicing_width = Param(pdt.TypeDouble, "Width of the chip dicing reference line", 10.0, unit="µm")
     chip_dicing_line_length = Param(pdt.TypeDouble, "Length of the chip dicing reference line", 100.0, unit="µm")
     chip_dicing_gap_length = Param(pdt.TypeDouble, "Gap between two chip dicing reference dashes", 50.0, unit="µm")
+    chip_dicing_in_base_metal = Param(pdt.TypeBoolean, "Insert chip dicing lines in base metal addition", False)
 
     def build(self):
         """Produces dicing edge, markers, labels and ground grid for the chip face."""
@@ -200,3 +201,5 @@ def _add_chip_dicing_line_dash(self, start, end, is_vertical, position):
         else:
             box = pya.DBox(start, position.y - self.chip_dicing_width/2, end, position.y + self.chip_dicing_width/2)
         self.cell.shapes(self.get_layer("chip_dicing")).insert(box)
+        if self.chip_dicing_in_base_metal:
+            self.cell.shapes(self.get_layer("base_metal_addition")).insert(box)