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  • Integrates riscv-gnu-toolchain (get-tool.sh) for baremetal, Linux, 32-bit, and 64-bit support, including newlib for diverse workloads.
  • Compiles Embench on baremetal for BBV generation, trace generation, and SimPoint analysis using Spike or QEMU.
    • Stores SimPoint results in /outputs/.
  • Introduces a modular baremetal environment with stubs for simplified workload porting, enabling direct jumps to main() or benchmark(). Includes emulator-specific stubs, entry points, linker script, and UART stdout support.
  • Enhances code modularity by organizing into separate files. Future improvement: leverage .cfg for easier _building_x_benchmark definitions and support workload-specific crt0.S and link.ld overrides.
  • Adds initial documentation in doc/.
  • Replaces old QEMU BBV flow with a unified flow.
  • Includes doc/emulator-comparison.md for detailed QEMU vs. Spike STF generation analysis. Alogn with a reproducible script.
  • Provides full_flow.py script for an interactive Docker-based workflow.
  • Adds board.cfg in environment for streamlined workload-specific flag and configuration declarations.

Next Steps:

  • Test riscv-tests on QEMU (baremetal) and other workloads.
  • Use SimPoint results to reduce workload traces.
  • Integrate with trace_archive.py for metadata storage and trace upload.
  • Run traces on Olympia (local generation or archive fetch).
  • Add comprehensive workloads like CoreMark.

@vinicius-r-silva
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vinicius-r-silva commented Aug 23, 2025

The amount of files in the docker_stf_trace_gen folder is making a litte confusing to identify the purpose of each script, I would suggest creating a sub folder for the files that needs to be used only once (Dockerfile, build-docker.sh, get-tools and the environment), and another folder for the test/example scripts (spike_vs_qemu.py, ...)

@Jatin-exe
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Jatin-exe commented Aug 25, 2025

@vinicius-r-silva Thanks for your review! I've made some improvements to the code, but there's still more to be done (e.g., better documentation and removing redundant lines/functions, PEP8 compliance ...). It's a work in progress. I've implemented the changes you suggested, as I had the same thoughts. I'd appreciate any additional feedback you have!

@jaksa-mips jaksa-mips self-requested a review September 4, 2025 16:03
@arupc arupc self-requested a review September 4, 2025 16:04
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per discussion in the meeting - approving

@jaksa-mips jaksa-mips merged commit 03e494a into riscv-software-src:master Sep 4, 2025
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3 participants