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riscv: telink:tl3218x: add ble optimize. #343

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merged 1 commit into from
Sep 14, 2024
Merged

riscv: telink:tl3218x: add ble optimize. #343

merged 1 commit into from
Sep 14, 2024

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haiwentelink
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@haiwentelink haiwentelink commented Sep 13, 2024 •
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  • add optimize for ble.
  • low down the ramcost.

@haiwentelink haiwentelink self-assigned this Sep 13, 2024
@haiwentelink haiwentelink force-pushed the telink_tl321x_with_ble branch 4 times, most recently from 72f9352 to d291b89 Compare September 13, 2024 10:56
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riscv: telink:tl3218x: add ble optimize.
15e60a5 
- add optimize for ble.
- low down the ramcost.
- revert nvs cache to pass certify.

Signed-off-by: Haiwen Xia <haiwen.xia@telink-semi.com>
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can not set the cache size to 8k , otherwise the tl3218x compile will fail for ram not enough . the lighting-app will open the ota, factorydata and shell , without shell is enough , but with shell will exceed 1312bytes .

@haiwentelink haiwentelink merged commit 45dc198 into telink_tl321x Sep 14, 2024
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@s07641069 s07641069 deleted the telink_tl321x_with_ble branch September 14, 2024 07:53
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