hal: telink: add support for 60M Mspi

- add clock setting for 60M mspi.
- select 60M mspi can save power.
- adjust power table for buteo and tercel.

Signed-off-by: Haiwen Xia <haiwen.xia@telink-semi.com>

Author: haiwentelink

boards/telink/tl721x/tl7218x-common.dtsi

@@ -125,7 +125,7 @@
 };
 
 &cpu0 {
-	clock-frequency = <60000000>;
+	clock-frequency = <80000000>;
 };
 
 &ram_ilm {

dts/riscv/telink/telink_tl721x.dtsi

@@ -21,7 +21,7 @@
 		#size-cells = <0>;
 		cpu0: cpu@0 {
 			reg = <0>;
-			clock-frequency = <60000000>;
+			clock-frequency = <80000000>;
 			compatible ="telink,tlx", "riscv";
 			riscv,isa = "rv32imac_zicsr_zifencei";
 			hlic: interrupt-controller {
@@ -81,7 +81,7 @@
 		power: power@80140180 {
 			compatible = "telink,tl721x-power";
 			reg = <0x80140180 0x40>;
-			power-mode = "LDO_0P94_LDO_1P8";
+			power-mode = "DCDC_0P94_DCDC_1P8";
 			vbat-type = "VBAT_MAX_VALUE_GREATER_THAN_3V6";
 			status = "okay";
 		};

soc/telink/tlsr/telink_tlx/init.ld

@@ -6,3 +6,4 @@
 
 . += CONFIG_ROM_START_OFFSET;
 KEEP(*(.init.*))
+KEEP(*(.flash_data))

soc/telink/tlsr/telink_tlx/soc.c

@@ -32,6 +32,7 @@
 #define CLK_60MHZ  60000000u
 #define CLK_80MHZ  80000000u
 #define CLK_120MHZ 120000000u
+#define CLK_240MHZ 240000000u
 #endif
 
 /* MID register flash size */
@@ -70,18 +71,19 @@
 
 /* Check System Clock value. */
 #if CONFIG_SOC_RISCV_TELINK_TL321X
-#if ((DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_24MHZ) && \
-	 (DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_48MHZ) && \
-	 (DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_96MHZ))
+#if ((DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_24MHZ) &&	  \
+	(DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_48MHZ) &&  \
+	(DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_96MHZ))
 #error "Invalid clock-frequency. Supported values: 24, 48, 96 MHz"
 #endif
 #elif CONFIG_SOC_RISCV_TELINK_TL721X
-#if ((DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_40MHZ) && \
-	 (DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_48MHZ) && \
-	 (DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_60MHZ) && \
-	 (DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_80MHZ) && \
-	 (DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_120MHZ))
-#error "Invalid clock-frequency. Supported values: 24, 40, 48, 60, 80 and 120 MHz"
+#if ((DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_40MHZ) &&	  \
+	(DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_48MHZ) &&  \
+	(DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_60MHZ) &&  \
+	(DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_80MHZ) &&  \
+	(DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_120MHZ) && \
+	(DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_240MHZ))
+#error "Invalid clock-frequency. Supported values: 24, 40, 48, 60, 80, 120, 240 MHz"
 #endif
 #endif
 
@@ -136,6 +138,13 @@ void soc_early_init_hook(void)
 	/* system init */
 	sys_init(POWER_MODE, VBAT_TYPE, INTERNAL_CAP_XTAL24M);
 
+#if CONFIG_SOC_RISCV_TELINK_TL721X
+	if (cclk == CLK_240MHZ) {
+		pm_set_dvdd(CORE_0P9V_SRAM_0P9V_BB_0P9V, DMA1, 1000);
+	}
+	pm_set_ret_ldo_voltage(RET_LDO_TRIM_0P65V);
+#endif
+
 #if CONFIG_PM
 	gpio_shutdown(GPIO_ALL);
 #endif /* CONFIG_PM */
@@ -162,12 +171,24 @@ void soc_early_init_hook(void)
 	case CLK_60MHZ:
 		PLL_240M_CCLK_60M_HCLK_60M_PCLK_15M_MSPI_48M;
 		break;
+	case CLK_80MHZ:
+		PLL_240M_CCLK_80M_HCLK_40M_PCLK_40M_MSPI_48M;
+		break;
 #endif /* CONFIG_SOC_RISCV_TELINK_TL721X */
+
 #if CONFIG_SOC_RISCV_TELINK_TL321X
 	case CLK_96MHZ:
 		PLL_192M_CCLK_96M_HCLK_48M_PCLK_48M_MSPI_48M;
 		break;
 #endif /* CONFIG_SOC_RISCV_TELINK_TL321X */
+#if CONFIG_SOC_RISCV_TELINK_TL721X
+	case CLK_120MHZ:
+		PLL_240M_CCLK_120M_HCLK_60M_PCLK_60M_MSPI_48M;
+		break;
+	case CLK_240MHZ:
+		PLL_240M_CCLK_240M_HCLK_120M_PCLK_120M_MSPI_48M;
+		break;
+#endif
 	}
 
 	/* Init Machine Timer source clock: 32 KHz RC */
@@ -224,12 +245,23 @@ void soc_tlx_restore(void)
 	case CLK_60MHZ:
 		PLL_240M_CCLK_60M_HCLK_60M_PCLK_15M_MSPI_48M;
 		break;
+	case CLK_80MHZ:
+		PLL_240M_CCLK_80M_HCLK_40M_PCLK_40M_MSPI_48M;
+		break;
 #endif /* CONFIG_SOC_RISCV_TELINK_TL721X */
 #if CONFIG_SOC_RISCV_TELINK_TL321X
 	case CLK_96MHZ:
 		PLL_192M_CCLK_96M_HCLK_48M_PCLK_48M_MSPI_48M;
 		break;
 #endif /* CONFIG_SOC_RISCV_TELINK_TL321X */
+#if CONFIG_SOC_RISCV_TELINK_TL721X
+	case CLK_120MHZ:
+		PLL_240M_CCLK_120M_HCLK_60M_PCLK_60M_MSPI_48M;
+		break;
+	case CLK_240MHZ:
+		PLL_240M_CCLK_240M_HCLK_120M_PCLK_120M_MSPI_48M;
+		break;
+#endif
 	}
 }
 

west.yml

@@ -239,7 +239,7 @@ manifest:
         - hal
     - name: hal_telink
       url: https://github.com/telink-semi/hal_telink
-      revision: d45ad1d5772528d8e3efc23fdcf8478cab7956f9
+      revision: 8e116bb74c344c043500425793d76c4d3ae21565
       path: modules/hal/telink
       groups:
         - hal