This repository is to help macOS and linux users who have just started learning verilog.

First steps with the Sipeed Tang Primer 20k FPGA.

Creating testbenches in Verilog is an essential practice to verify the functionality of your modules and ensure your design behaves as expected.

This project implements a BCD (Binary-Coded Decimal) converter that reads DIP switch input and controls a 7-segment display, showing digits 0–8 or ‘E’ for invalid combinations.