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[cpu] riscv64: update intrinsics #2929

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[cpu] riscv64: update intrinsics #2929

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8d88e39
riscv64: update intrinsics
zhangfeiv0 Mar 21, 2025
ee0eb52
riscv64: fix clang-format error
zhangfeiv0 Mar 21, 2025
62313a2
riscv64: fix clang-format error
zhangfeiv0 Mar 21, 2025
43e1b4a
riscv64: fix clang-format error
zhangfeiv0 Mar 21, 2025
204aa34
riscv64: update cmake
zhangfeiv0 Mar 21, 2025
ffbffff
riscv64: update cmake
zhangfeiv0 Mar 22, 2025
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12 changes: 10 additions & 2 deletions cmake/platform.cmake
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Original file line number Diff line number Diff line change
Expand Up @@ -464,10 +464,18 @@ endif()
if (DNNL_TARGET_ARCH STREQUAL "RV64")
# Check if the RVV Intrinsics can be compiled with the current toolchain and flags
include(CheckCXXSourceCompiles)
check_cxx_source_compiles("#include <riscv_vector.h>
check_cxx_source_compiles("#if !defined(__riscv) || !defined(__riscv_v)
#error \"RISC-V or vector extension(RVV) is not supported by the compiler\"
#endif
#if defined(__riscv_v_intrinsic) && __riscv_v_intrinsic < 12000
#error \"Wrong intrinsics version, v0.12 or higher is required for gcc or clang\"
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Suggested change
#error \"Wrong intrinsics version, v0.12 or higher is required for gcc or clang\"
#error \"RISC-V intrinsics v0.12 or higher is required\"

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Done.

#endif
#include <riscv_vector.h>
int main() {
size_t size = 64;
return vsetvl_e32m2(size);
return __riscv_vsetvl_e32m2(size);
};"
CAN_COMPILE_RVV_INTRINSICS
)
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27 changes: 14 additions & 13 deletions src/cpu/rv64/rvv_nchw_pooling.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -57,9 +57,9 @@ void MaxPooling(const float *src, float *dst, const dim_t batch,
int ow_offset = ow * strideW - padLeft;
size_t size = std::min(ow_offset + kerW, inW)
- std::max(ow_offset, 0);
size_t cycleLength = vsetvl_e32m8(size);
vfloat32m8_t vmax
= vle32_v_f32m8(&arr_flt_min[0], cycleLength);
size_t cycleLength = __riscv_vsetvl_e32m8(size);
vfloat32m8_t vmax = __riscv_vle32_v_f32m8(
&arr_flt_min[0], cycleLength);

for (int id = std::max(od_offset, 0);
id < std::min(od_offset + kerD, inD); id++)
Expand All @@ -73,34 +73,35 @@ void MaxPooling(const float *src, float *dst, const dim_t batch,
size_t iw = 0;
for (; iw < size - cycleLength;
iw += cycleLength) {
vfloat32m8_t vsrc = vle32_v_f32m8(
vfloat32m8_t vsrc = __riscv_vle32_v_f32m8(
&local_src[local_src_offset + iw],
cycleLength);
vmax = vfmax_vv_f32m8(
vmax = __riscv_vfmax_vv_f32m8(
vsrc, vmax, cycleLength);
}

size_t tailLength = vsetvl_e32m8(size - iw);
size_t tailLength
= __riscv_vsetvl_e32m8(size - iw);
{
vfloat32m8_t vsrc = vle32_v_f32m8(
vfloat32m8_t vsrc = __riscv_vle32_v_f32m8(
&local_src[local_src_offset + iw],
tailLength);
vmax = vfmax_vv_f32m8(
vmax = __riscv_vfmax_vv_f32m8(
vsrc, vmax, tailLength);
}
}

vfloat32m1_t min_scalar;
float min = -__FLT_MAX__;
min_scalar = vle32_v_f32m1(&min, 1);
min_scalar = __riscv_vle32_v_f32m1(&min, 1);

cycleLength = vsetvl_e32m8(size);
cycleLength = __riscv_vsetvl_e32m8(size);
vfloat32m1_t vred_res;
vred_res = vfredmax_vs_f32m8_f32m1(
vred_res, vmax, min_scalar, cycleLength);
vred_res = __riscv_vfredmax_vs_f32m8_f32m1(
vmax, min_scalar, cycleLength);

float red_res;
vse32_v_f32m1(&red_res, vred_res, 1);
__riscv_vse32_v_f32m1(&red_res, vred_res, 1);
dst[dst_offset] = red_res;
}
}
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