drivers: ethernet: Add Xilinx AXI Enet driver #73986

WorldofJARcraft · 2024-06-10T08:05:05Z

The Xilinx AXI Ethernet subsystem is commonly found in FPGA designs. This patch adds a driver and device tree bindings for the Ethernet MAC core.
The driver was tested on a RISC-V softcore in an FPGA design, with an RGMII phy and Ethernet subsystem version 7.2 Rev. 14. Device tree bindings match the device tree generated by Vitis hsi. Note that Vitis generates one of the two included compatible strings depending on version.
Please not that TX checksum offloading depends on #73985.

WorldofJARcraft · 2024-06-17T08:35:20Z

Note that the Ethernet MAC driver depends on the Ethernet MDIO and the AXI DMA drivers.

saizen408 · 2024-07-31T11:07:18Z

drivers/ethernet/Kconfig.xilinx_axienet

+	bool "Xilinx AXI Ethernet Driver"
+	default y
+	depends on DT_HAS_XLNX_AXI_ETHERNET_7_2_ENABLED || DT_HAS_XLNX_AXI_ETHERNET_1_00_A_ENABLED
+	depends on DT_HAS_XLNX_ETH_DMA_ENABLED && XILINX_AXI_DMA


Is XILINX_AXI_DMA supposed to be DMA_XILINX_AXI_DMA? @WorldofJARcraft

Yes, it seems like I forgot to change this in this pull request.

decsny · 2024-08-01T14:23:19Z

drivers/ethernet/Kconfig.xilinx_axienet

+	depends on DT_HAS_XLNX_ETH_DMA_ENABLED && DMA_XILINX_AXI_DMA
+	help
+		Enable Xilinx 1G / 2.5G AXI Ethernet driver,
+		commonly found on FPGAs. Depends on Xilinx AXI DMA.


very minor nit but the dependency should already be visible in the menu, don't think it's needed to clarify in the help string.

OK, removed it.

drivers/ethernet/eth_xilinx_axienet.c

decsny · 2024-08-01T14:24:51Z

drivers/ethernet/eth_xilinx_axienet.c

+#define LOG_MODULE_NAME eth_xilinx_axienet
+#define LOG_LEVEL       CONFIG_ETHERNET_LOG_LEVEL
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(LOG_MODULE_NAME);


nit but please do the log module register as one line (it can take two arguments for the name and level, dont need to define macros)

decsny · 2024-08-01T14:26:36Z

drivers/ethernet/eth_xilinx_axienet.c

+#define XILINX_AXIENET_UNICAST_ADDRESS_WORD_0_OFFSET 0x00000700
+#define XILINX_AXIENET_UNICAST_ADDRESS_WORD_1_OFFSET 0x00000704
+
+#define ETH_ALEN 6


NET_ETH_ADDR_LEN macro already exists, please use that

Done, must have overlooked this.

decsny · 2024-08-01T14:30:00Z

drivers/ethernet/eth_xilinx_axienet.c

+	(void)ethdev;
+	if (status < 0) {
+		LOG_ERR("DMA RX error: %d", status);
+		k_panic();


is a dma error code worth causing a kernel panic?

I do not insist on the panic.
The Xilinx DMA only errors when it was configured incorrectly (e.g., invalid address), so I found this helpful in debugging.
Is there some define I can guard this with?

decsny · 2024-08-01T14:32:36Z

drivers/ethernet/eth_xilinx_axienet.c

+
+		if (!pkt) {
+			LOG_ERR("Could not allocate a packet!");
+		} else {


same comment about the else block

Panic removed.

decsny · 2024-08-01T14:32:46Z

drivers/ethernet/eth_xilinx_axienet.c

+				LOG_ERR("Could not write RX buffer into packet!");
+				k_panic();
+				net_pkt_unref(pkt);
+			} else {


ditto else block

Guard with ifdef?

decsny · 2024-08-01T14:32:56Z

drivers/ethernet/eth_xilinx_axienet.c

+				if (net_recv_data(data->interface, pkt) < 0) {
+					LOG_ERR("Coult not receive packet data!");
+					net_pkt_unref(pkt);
+				} else {


ditto else block

Guard with ifdef?

decsny · 2024-08-01T14:33:03Z

drivers/ethernet/eth_xilinx_axienet.c

+		} else {
+			if (net_pkt_write(pkt, data->rx_buffer, packet_size)) {
+				LOG_ERR("Could not write RX buffer into packet!");
+				k_panic();


ditto kernel panic question, and for all other occurrences in the file

decsny · 2024-08-01T14:33:55Z

drivers/ethernet/eth_xilinx_axienet.c

+	struct device *ethdev = (struct device *)user_data;
+	struct xilinx_axienet_data *data = ethdev->data;
+
+	(void)data;


what does this accomplish

removing change request because the comments mostly addressed, the panic still seems like a bad idea to me but I don't have a stake in this driver so it's up to author

saizen408 · 2024-08-27T23:12:08Z

@WorldofJARcraft Is it on purpose that zephyr_library_sources_ifdef(CONFIG_XILINX_AXI_ENET eth_xilinx_axi_enet.c) is not included in zephyr/drivers/ethernet/CMakeLists.txt ?

I'm fairly new to zephyr so forgive if I am missing something.

robhancocksed · 2025-03-19T19:55:53Z

@WorldofJARcraft It looks like this branch has some trivial conflicts with the main branch that need resolving. Aside from that, unless you are planning any more changes I think you could remove the Draft status to open this for more review?

WorldofJARcraft · 2025-03-20T07:42:14Z

@robhancocksed I will fix the merge conflicts and make this PR ready for review.
I was actually waiting for feedback on my proposed API change (#82349). However, I am also happy to merge the branch as-is and change the API later.

drivers/ethernet/CMakeLists.txt

drivers/ethernet/eth_xilinx_axienet.c

WorldofJARcraft · 2025-03-20T12:55:47Z

I have force-pushed an untested commit with the changes suggested by @maass-hamburg.
I will build and test the driver manually later today.

WorldofJARcraft · 2025-03-20T16:00:01Z

I have fixed a minor issue with the phy_link_state_changed callback and tested the driver on my RISC-V testbed.

drivers/ethernet/eth_xilinx_axienet.c

drivers/ethernet/CMakeLists.txt

drivers/ethernet/eth_xilinx_axienet.c

dts/bindings/ethernet/xlnx,axi-ethernet-1.00.a.yaml

The Xilinx AXI Ethernet subsystem is commonly found in FPGA designs. This patch adds a driver and device tree bindings for the Ethernet MAC core and its MDIO controller. The driver was tested on a RISC-V softcore in an FPGA design, with an RGMII phy and Ethernet subsystem version 7.2 Rev. 14. Device tree bindings match the device tree generated by Vitis hsi. Note that Vitis generates one of the two included compatible strings depending on version. Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>

robhancocksed · 2025-03-21T19:53:21Z

drivers/ethernet/eth_xilinx_axienet.c

+		(data->rx_completed_buffer_index + 1) % CONFIG_ETH_XILINX_AXIENET_BUFFER_NUM_RX;
+	size_t current_descriptor = data->rx_completed_buffer_index;
+
+	if (!net_if_is_up(data->interface)) {


You probably want to do this after updating rx_completed_buffer_index, otherwise the indexes won't be tracked properly across a down/up cycle..

zephyrbot added the area: Ethernet label Jun 10, 2024

WorldofJARcraft mentioned this pull request Jun 10, 2024

drivers: dma: Add Xilinx AXI DMA driver #73926

Merged

zephyrbot added area: Devicetree Binding PR modifies or adds a Device Tree binding platform: Xilinx Xilinx labels Jun 10, 2024

zephyrbot requested review from decsny, galak, henrikbrixandersen, ibirnbaum, lmajewski and pdgendt June 10, 2024 08:05

WorldofJARcraft marked this pull request as draft June 10, 2024 09:40

WorldofJARcraft force-pushed the xilinx-axienet-mac branch 2 times, most recently from bce8faf to b8dde37 Compare June 10, 2024 16:00

WorldofJARcraft mentioned this pull request Jun 11, 2024

net: Support partial checksum offloading #73985

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boards: openhwgroup: add CV64A6 on GenesysII board #77734

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kartben merged commit 4342d71 into zephyrproject-rtos:main Mar 24, 2025
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drivers: ethernet: Add Xilinx AXI Enet driver #73986

drivers: ethernet: Add Xilinx AXI Enet driver #73986

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